ZPSD211RL View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
ZPSD211RL Datasheet PDF : 51 Pages
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PSD211R Family
10.0
I/O Port
Functions
The PSD211R has three I/O ports (Ports A, B, and C) that are configurable at the bit level.
This permits great flexibility and a high degree of customization for specific applications.
The next section describes the control registers for the ports. Following that are sections
that describe each port. Figures 5 through 7 show the structure of Ports A through C,
respectively.
Note: any unused inputs should be connected directly to ground or pulled up to VCC (using
a 10KΩ to 100KΩ resistor).
10.1 CSIOPORT Registers
Control of the ports is primarily handled through the CSIOPORT registers. There are 24
bytes in the address space, starting at the base address labeled CSIOPORT. Since the
PSD211R uses internal address lines A15-A11 for decoding, the CSIOPORT space
will occupy 2 Kbytes of memory, on a 2 Kbyte boundary. This resolution can be improved
to reduce wasted address space by connecting lower order address lines (A10 and below)
to Port C. Using this method, resolution down to 256 Kbytes may be achieved. The
CSIOPORT space must be defined in your PSDsoft design file. The following tables list
the registers located in the CSIOPORT space.
Table 5. CSIOPORT Registers for 8-Bit Data Busses
Register Name
Port A Pin Register
Port A Direction Register
Port A Data Register
Port B Pin Register
Port B Direction Register
Port B Data Register
Power Management Register (Note 1)
Offset (in hex)
from CSIOPORT
Base Address
+2
+4
+6
+3
+5
+7
+10
NOTE: 1. ZPSD only.
Type of
Access
Allowed
Read
Read/Write
Read/Write
Read
Read/Write
Read/Write
Read/Write
10.2 Port A (PA0-PA7)
MCU I/O Mode
The default configuration of Port A is MCU I/O. In this mode, every pin can be set
(at run-time) as an input or output by writing to the respective pin’s direction flip-flop
(DIR FF, Figure 5). As an output, the pin level can be controlled by writing to the respective
pin’s data flip-flop (DFF, Figure 5A). The Pin Register can be read to determine logic level
of the pin. The contents of the pin register indicate the true state of the PSD driving the pin
through the DFF or an external source driving the pin.
12
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