ZPSD211RVL View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
ZPSD211RVL Datasheet PDF : 51 Pages
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10.0
I/O Port
Functions
(Cont.)
PSD211R
10.2 Port A (PA0-PA7) (Cont.)
Latched Address Output Mode
Alternatively, any bit(s) of Port A can be configured to output a low-order demultiplexed
address bus bit. The address is provided by the internal PSD address latch, which latches
the address on the trailing edge of ALE/AS. Port A then outputs the desired demultiplexed
address bits. This feature can eliminate the need for an external latch (for example:
74LS373) if you have devices that require low-order latched address bits. Although any pin
of Port A may output an address signal, the pin is position-dependent. In other words, pin
PA0 of Port A may only pass A0, PA1 only A1, and so on.
The control registers of Port A are located in CSIOPORT space; see Table 5. Each pin of
Port A can be individually configured. The following table summarizes what the control
registers (in CSIOPORT space) for Port A do:
Register Name
Port A Pin Register
Port A Direction Register
Port A Data Register
0 Value
Sampled logic level
at pin = ‘0’
Pin is configured
as input
Data in DFF = ‘0’
NOTE: 1. Default value is the value after reset.
Figure 5. Port A Pin Structure
1 Value
Sampled logic level
at pin = ‘1’
Pin is configured
as output
Data in DFF = ‘1’
Default
Value
(Note 1)
X
0
0
I
N
T
E
R
READ DATA
N
A
L
A
WRITE DATA CK
D
DFF
D
R
DR
/
D
A
ALE
G
T
LATCH
A
D
R
B
U
S
READ DIR
A
D
0
/
A
D
7
RESET
D DIR
WRITE DIR CK FF
R
MCU
I/O
OUT
LATCHED
ADDR
OUT
READ PIN
MUX
CONTROL
PORT A PIN
ENABLE
13
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