ZPSD211RL View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ZPSD211RL

Low Cost Field Programmable Microcontroller Peripherals

STMicroelectronics 

12.

Control Signals

(Cont.)

PSD211R Family

Table 8A. External PSD Signal States During and Just After Reset

Port

AD0/A0-

AD15/A15

Port Pins

PA0-PA7

Port Pins

PB0-PB7

Port Pins

PC0-PC2

Configured Mode of Operation

Signal State Just

Signal State After Reset

During Reset

(Note 1)

All

Input (Hi-Z)

MCU address

and/or data

MCU I/O

Input (Hi-Z)

Input (Hi-Z)

PSD211R,

Latched Address Out ZPSD211R

Logic 0

MCU address

ZPSD211RV

Hi-Z

MCU address

MCU I/O

Input (Hi-Z

Input (Hi-Z)

Chip Select Outputs,

CS0-CS7, CMOS

PSD211R,

ZPSD211R

ZPSD211RV

Logic 1

Hi-Z

Per CS equations

Per CS equations

Chip Select Outputs,

PSD211R,

ZPSD211R

Hi-Z

CS0-CS7, Open Drain

ZPSD211RV

Hi-Z

Per CS equations

Per CS equations

Address or Logic Inputs, A16-A18

Input (Hi-Z)

Input (Hi-Z)

Chip Select Outputs,

CS8-CS10, CMOS

PSD211R,

ZPSD211R

ZPSD211RV

Logic 1

Hi-Z

Per CS equations

Per CS equations

NOTE: 1. Signal is valid immediately after reset for non-V devices. ZPSD211RV devices need an additional

500 nsec after reset before signal is valid.

Table 8B. Internal PSD Signal States During and Just After Reset

Component

Internal Signal

State During

Internal Signal

Reset

Internal

Signal State

During

Power-Down

PAD A and PAD B

All registers in CSIOPORT

address space, including:

 Direction

 Data

 PMR (turbo bit, ZPSD only)

CS0-CS10

CSIOPORT,

ES0-ES7

N/A

Logic 1 (inactive) Per CS Equations

Logic 0 (inactive)

Per equations

for each

internal signal

Logic 0 in all bit of Logic 0 until

all registers changed by MCU

NOTE: N/A = Not Applicable

Figure 8. The Required Reset Cycle for ZPSD211RV Devices Only.

VIH

VIL

500 ns

RESET LOW

500 ns

RESET HIGH

ZPSD211R(V)

IS OPERATIONAL

19

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