ZPSD211RL View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
ZPSD211RL Datasheet PDF : 51 Pages
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15.0
Security Mode
PSD211R Family
Security Mode in the PSD211R locks the contents of PAD A, PAD B, and all the
configuration bits. The EPROM and I/O contents can be accessed only through the PAD.
The Security Mode must be set by PSDsoft prior to run-time. The Security Bit can only be
erased on the UV parts using a full-chip erase. If Security Mode is enabled, the contents of
the PSD211R can not be uploaded (copied) on a device programmer.
16.0
Power
Management
PSDs from all 211R families use zero-power memory techniques that place memory into
Standby Mode between MCU accesses. The memory becomes active briefly after an
address transition, then delivers new data to the outputs, latches the outputs, and returns to
Standby. This is done automatically and the designer has to do nothing special to benefit
from this feature.
In addition to the benefits of Zero-power memory technology, there are ways to gain
additional savings. The following factors determine how much current the entire PSD device
uses:
• Use of CSI (Chip Select Input)
• Setting of the CMiser bit
• Setting of the Turbo Bit (ZPSD only)
• The number of product terms used in the PAD
• The composite frequency of the input signals to the PAD
• The loading on I/O pins.
The total current consumption for the PSD is calculated by summing the currents from
memory, PAD logic, and I/O pins, based on your design parameters and the power
management options used.
16.1 CSI Input
Driving the CSI pin inactive (logic 1) disables the inputs of the PSD and forces the entire
PSD to enter Power-down Mode, independent of any transition on the MCU bus (address
and control) or other PSD inputs. During this time, the PSD device draws only standby
current (micro-amps). Alternately, driving a logic 0 on the CSI pin returns the PSD to normal
operation. See Tables 7A and 7B for information on signal states during Power-down Mode.
The CSI pin feature is available only if enabled in the PSDsoft Configuration utility.
16.2 CMiser bit
In addition to power savings resulting from the Zero-power technology used in the memory,
the CMiser feature saves even more power under certain conditions. Savings are
significant when the PSD is configured for an 8-bit data path because the CMiser feature
turns off half of the array when memory is being accessed (the memory is divided internally
into odd and even arrays). See the DC characteristics table for current usage related to the
CMiser bit.
You should keep the following in mind when using this bit:
• Setting of this bit is accomplished with PSDsoft at the design stage, prior to run-time.
• Memory access times are extended by 10 nsec for standard voltage (non-V) devices,
and 20 nsec for low voltage (V) devices.
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