PSD511B1-C-90UI View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
PSD511B1-C-90UI Datasheet PDF : 153 Pages
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PSD5XX Family
13.7 AC/DC Parameters – ZPLD Timing Parameters (5 V ± 10% Versions)
Combinatorial Delays (5 V ± 10% Versions)
Symbol
Parameter
t PD
I/O Input or Feedback to
Combinatorial Output
t RPD
Registered Input to
Combinatorial Output
t EA
Input to Output Enable
t ER
Input to Output Disable
t ARP
Register Clear or Preset
Delay
t ARPW
Register Clear or Preset
Pulse Width
t ARD
Array Delay
Conditions
Port B, E
(Note 1)
Any Input
Any Input
Any Input
Any Input
-70
-90**
-15
ZPLD_TURBO
Min Max Min Max Min Max OFF* Unit
25
30
34 Add 10 ns
27
32
36 Add 10 ns
25
28
32 Add 10 ns
25
28
32 Add 10 ns
27
30
34 Add 10 ns
20
25
29
ns
16
18
22
ns
NOTE: 1. Ports A, C, D and latched address from ADIO (A0, A1, A8-A15).
**If ZPLD_TURBO is off and the ZPLD is operating above 15 MHz, there is no need to add 10 ns to the timing parameters.
**The -90 speed is available only on Industrial Temperature Range product.
Synchronous Clock Mode (5 V ± 10%)
Symbol
Parameter
Conditions
-70
-90**
-15
ZPLD_TURBO
Min Max Min Max Min Max OFF* Unit
Maximum Frequency
External Feedback
1/(tS + tCO)
30.30
27.03
25.00
f MAX
Maximum Frequency
Internal Feedback (fCNT)
1/(tS + tCO –10)
Maximum Frequency
Pipelined Data
1/(tCH + tCL)
43.48
50.00
37.04
41.67
31.25
35.71
tS
Input Setup Time
Any Input
15
17
20
tH
Input Hold Time
Any Input
0
0
0
t CH
Clock High Time
Clock Input
10
12
15
t CL
Clock Low Time
Clock Input
10
12
15
t CO
Clock to Output Delay Clock Input
18
20
22
t ARD
Array Delay for Product
Term Expansion
Any Macrocell
16
18
22
Add 10
0
0
0
0
0
tMIN Minimum Clock Period t CH + t CL
20
24
29
0
**If ZPLD_TURBO is off and the ZPLD is operating above 15 MHz, there is no need to add 10 ns to the timing parameters.
**The -90 speed is available only on Industrial Temperature Range product.
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
113
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