PSD511B1-C-90UI View Datasheet(PDF) - STMicroelectronics
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Description
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PSD511B1-C-90UI Datasheet PDF : 153 Pages
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13.8 Microcontroller Interface – AC/DC Parameters (5 V ± 10% Versions)
PSD5XX Family
Explanation of AC Symbols for Non ZPLD Timing.
Example:
t AVLX Time from Address Valid to ALE Invalid.
A – Address
C – Power Down
D– Input Data
E– E
H – Logic Level High
I – Interrupt
L – Logic Level Low or ALE
N – Reset
P – Port Signal
Q – Output Data
R – WR, UDS, LDS, DS, IORD, PSEN
S – Chip Select
T – R/W
t – Time
V – Valid
X – No Longer a Valid Logic Level
Z – Float
Read Timing (5 V ± 10% Versions)
Symbol
Parameter
-70
-90*
-15 EPROM_CMiser
Conditions Min Max Min Max Min Max
ON
Unit
t LVLX
t AVLX
t LXAX
t AVQV
ALE or AS Pulse Width
Address Setup Time (Note 4)
Address Hold Time
(Note 4)
Address Valid to Data
Valid
(Note 4)
18
20
28
5
6
10
7
8
11
0
ns
0
ns
0
ns
70
90
150
Add 10
ns
t SLQV
CS Valid to Data Valid
RD to Data Valid
8/16-Bit Bus
(Note 1)
80
100
150
Add 10
ns
20
32
40
0
ns
t RLQV
RD to Data Valid 8-Bit
Bus, 8031 Separate
Mode
(Note 2)
32
38
45
0
ns
RD to Data Valid from (Note 3)
Interrupt Controller
32
38
45
0
ns
t RHQX
t RLRH
t RHQZ
t EHEL
t THEH
RD Data Hold Time
RD Pulse Width
RD to Data High-Z
E Pulse Width
R/W Setup Time
to Enable
(Note 1)
(Note 1)
(Note 1)
0
0
0
0
ns
30
32
38
0
ns
22
25
33
0
ns
30
32
38
0
ns
8
10
18
0
ns
t ELTL
R/W Hold Time After
Enable
0
0
0
0
ns
In 16-Bit Data Bus
tAVPV Address Input Valid to Mode (Note 5)
20
30
38
0
ns
Address Output Delay In 8-Bit Data Bus
Mode (Note 5)
22
32
48
0
ns
NOTES: 1. RD timing has the same timing as PSEN, DS, LDS, UDS signals.
2. RD and PSEN have the same timing for 8031 mode.
3. Read to Data Valid of the Interrupt Request Latch and Interrupt Priority Status. RD timing has the same timing as PSEN, DS,
LDS, UDS signals.
4. Any input used to select an internal PSD5XX function.
5. In multiplexed mode latched address generated from ADIO delay to address output on any Port.
*The -90 speed is available only on Industrial Temperature Range product.
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