ST92P141K4D0 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST92P141K4D0

8/16-BIT MCU FOR 3-PHASE AC MOTOR CONTROL

STMicroelectronics 

ST92141 - 3-PHASE INDUCTION MOTOR CONTROLLER (IMC)

INDUCTION MOTOR CONTROLLER (Cont’d)

7.4.3.1 Input and Output pins

– Input Pin

TACHO: Signal input from a tachogenerator for

measuring the rotor speed.

NMI: Input signal for disabling the IMC output

and sending an interrupt request to the ST9

core.

– Output Pins

UH, UL, VH, VL, WH, WL: 3-Phase PWM sig-

nals and complementary signals (dedicated

pins, refer to device Pin Description).

Note: The INTCLK signal is the internal clock of

the ST9 microcontroller (system clock).

7.4.3.2 Rotor Speed Measurement

The TACHO signal is input from a Schmitt trigger

port. When a rising and/or falling edge occurs (pro-

grammable edge sensitivity), the IMC controller

does the following:

– Captures the 16-bit Tacho Counter

– Clears the Tacho Counter (if CCPT bit is set)

– Generates a CPT interrupt

The 16-bit Tacho Counter clock is derived from the

clock used by the PWM Counter, through a 12-bit

prescaler. The 12-bit prescaler divides by 1, 2, 3,

......, 4096.

If no edge occurs on the TACHO signal or the

event sensitivity is disabled (see Table 25) and the

16-bit counter is running, an OTC overflow inter-

rupt will be issued when the MSB (Most Significant

Byte) of the Tacho Counter reaches the Tacho

Compare register value.

7.4.3.3 Three-Phase PWM Generator

The 3-Phase PWM signal is generated using a 10-

bit PWM Counter and three 11-bit Compare regis-

ters one for each phase (U, V, W).

The 10-bit PWM Counter clock is supplied through

a 8-bit prescaler (dividing by 1, 2, 3, .., 256).

It can work in Zerocentered mode or in Classical

mode. The mode is selected by the CMS bit in the

PCR0 register:

Zerocentered Mode

In this operating mode, the PWM Counter counts

up to the value loaded in the 10-bit Compare 0 reg-

ister then counts down until it reaches zero and re-

starts counting up.

Classical Mode

In this operating mode, the PWM Counter counts

up to the value loaded in the 10-bit Compare Reg-

ister. Then the PWM Counter is cleared and it re-

starts counting up.

Figure 64 shows the counting sequence in Classi-

cal and Zerocentered mode.

PWM signal generation in Zerocentered mode

In this mode, all three PWM signals are set to ‘0’

when the PWM Counter reaches, in up-counting,

the corresponding 11-bit Compare register value

and they are set to ‘1’ when the PWM Counter

reaches the 11-bit Compare value again in down-

counting.

The comparison is performed between the PWM

Counter value extended to 11 bits and the 11-bit

Compare register (either in Zerocentered or in

Classical mode).

Figure 64. Counting sequence in Zerocentered and Classical mode

Zerocentered

mode

0

1

2

.... 15 16 15 ....

2

1

0

1

T

Classical mode 0

1

2

..... 15 16

0

1

..... 16

0

1

T

T = PWM period, Value of 10-bit Compare Register= 16

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