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ST92P141K4D0 View Datasheet(PDF) - STMicroelectronics

Part Name
Description
Manufacturer
ST92P141K4D0
ST-Microelectronics
STMicroelectronics 
ST92P141K4D0 Datasheet PDF : 179 Pages
First Prev 171 172 173 174 175 176 177 178 179
ST92141 - ELECTRICAL CHARACTERISTICS
IMC TIMING TABLE
VDD = 5V ± 10%, TA = 40°C to +85°C, CLoad = 50pF, fINTCLK = 25MHz, unless otherwise specified)
N° Symbol
Parameter
Value (Note)
Formula(1)
Min
Unit
Max
1 TwTACLR
Tacho Low Level Minimum Pulse Width in Rising
Edge Mode
Tck
40
ns
2 TwTACHR
Tacho High Level Minimum Pulse Width in Ris-
ing Edge Mode
Tck
40
ns
3 TwTACHF
Tacho High Level Minimum Pulse Width in Fall-
ing Edge Mode
Tck
40
ns
4 TwTACLF
Tacho Low Level Minimum Pulse Width in Fall-
ing Edge Mode
Tck
40
ns
5 TwNMILR
NMI Low Level Minimum Pulse Width in Rising
Edge Mode
1000
ns
6 TwNMIHR
NMI High Level Minimum Pulse Width in Rising
Edge Mode
1000
ns
7 TwNMIHF
NMI High Level Minimum Pulse Width in Falling
Edge Mode
1000
ns
8 TwNMILF
NMI Low Level Minimum Pulse Width in Falling
Edge Mode
1000
ns
9 TdPHZ
Delay from NMI to Phases in High Impedance
1000
ns
Note: The value in the left hand column shows the formula used to calculate the minimum or maximum timing from the oscillator clock period.
The value in the right hand two columns show the minimum and maximum timing for an internal clock at 25MHz (INTCLK).
Measurement points are taken with reference to VIH-VIH for positive pulse and VIL-VIL for negative pulse
(1) Formula guaranteed by design.
Legend:
Tck = INTCLK period = OSCIN period when OSCIN is not divided by 2;
2 x OSCIN period when OSCIN is divided by 2;
OSCIN period x PLL factor when the PLL is enabled.
IMC TIMING
TACHO
NMI
5
6
/
NMI
UH/UL/VH/VL/WH/WL
7
8
9
173/179
1

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