ST92F120R1Q7 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
ST92F120R1Q7 Datasheet PDF : 324 Pages
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ST92F120 - SINGLE VOLTAGE FLASH & EEPROM
REGISTER DESCRIPTION (Cont’d)
3.3.2 Status Registers
During a Flash or an EEPROM write operation any
attempt to read the memory under modification will
output invalid data (FFh equivalent to a NOP in-
struction). This means that the Flash memory is
not fetchable when a write operation is active: the
write operation commands must be given from an-
other memory (EEPROM, internal RAM, or exter-
nal memory).
Two Status Registers (FESR[1:0] are available to
check the status of the current write operation in
Flash and EEPROM memories.
FLASH & EEPROM STATUS REGISTER 0
(FESR0)
Address: 224002h -Read/Write
Reset value: 0000 0000 (00h)
7
6
5
4
3
2
1
0
FEER FESS FESS FESS FESS FESS FESS FESS
R
6
5
4
3
2
1
0
Bit 7 = FEERR: Flash or EEPROM write ERRor
(Read/Write).
This bit is set by hardware when an error occurs
during a Flash or an EEPROM write operation. It
must be cleared by software.
0: Write OK
1: Flash or EEPROM write error
Bits 6:0 = FESS[6:0]. Flash and EEPROM Status
Sector 6-0 (Read Only).
These bits are set by hardware and give the status
of the 7 Flash and EEPROM sectors (TF, E1, E0,
F3, F2, F1, F0). The meaning of FESSx bit for sec-
tor x is given by the following table:
Table 9. FESSx bit Values
FEERR
FBUSY
EBUSY
FSUSP
1
-
-
0
1
-
FESSx=1
meaning
Write Error in
Sector x
Write operation
on-going in sec-
tor x
Table 9. FESSx bit Values
FEERR
FBUSY
EBUSY
FSUSP
0
0
1
0
0
0
FESSx=1
meaning
Sector Erase
Suspended in
sector x
Don’t care
FLASH & EEPROM STATUS REGISTER 1
(FESR1)
Address: 224003h -Read Only
Reset value: 0000 0000 (00h)
7
6
5
4
3
2
1
0
ERER PGER
SWE
R
Bit 7 = ERER. Erase error (Read Only).
This bit is set by hardware when an Erase error oc-
curs during a Flash or an EEPROM write opera-
tion. This error is due to a real failure of a Flash
cell, that can not be erased anymore. This kind of
error is fatal and the sector where it occurred must
be discarded (if it was in one of the EEPROM sec-
tors, the hardware emulation can not be used any-
more). This bit is automatically cleared when bit
FEERR of the FESR0 register is cleared by soft-
ware.
0: Erase OK
1: Erase error
Bit 6 = PGER. Program error (Read Only).
This bit is automatically set when a Program error
occurs during a Flash or an EEPROM write opera-
tion. This error is due to a real failure of a Flash
cell, that can not be programmed anymore. The
byte where this error occurred must be discarded
(if it was in the EEPROM memory, the byte must
be reprogrammed to FFh and then discarded, to
avoid the error occurring again when that byte is
internally moved). This bit is automatically cleared
when bit FEERR of the FESR0 register is cleared
by software.
0: Program OK
1: Flash or EEPROM Programming error
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