ST92F120R1Q7 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST92F120R1Q7

8/16-BIT FLASH MCU FAMILY WITH RAM, EEPROM AND J1850 BLPD

STMicroelectronics 

ST92F120 - SINGLE VOLTAGE FLASH & EEPROM

REGISTER DESCRIPTION (Cont’d)

Bit 5 = SWER. Swap or 1 over 0 Error (Read On-

ly).

This bit has two different meanings, depending on

whether the current write operation is to Flash or

EEPROM memory.

In Flash memory, this bit is automatically set when

trying to program at 1 bits previously set at 0 (this

does not happen when programming the Protec-

tion bits). This error is not due to a failure of the

Flash cell, but only flags that the desired data has

not been written.

In the EEPROM memory, this bit is automatically

set when a Program error occurs during the swap-

ping of the unselected pages to the new sector

when the old sector is full (see Section 3.5.1 Hard-

ware EEPROM Emulation for more details).

This error is due to a real failure of a Flash cell,

that can not be programmed anymore. When this

error is detected, the embedded algorithm auto-

matically exits the Page Update operation at the

end of the Swap phase, without performing the

Erase Phase 0 on the full sector. In this way the

old data are kept, and through predefined routines

in TestFlash (Find Wrong Pages = 230029h and

Find Wrong Bytes = 23002Ch), the user can com-

pare the old and the new data to find where the er-

ror occurred.

Once the error has been discovered the user must

take to end the stopped Erase Phase 0 on the old

sector (through another predefined routine in Test-

Flash: Complete Swap = 23002Fh). The byte

where the error occurred must be reprogrammed

to FFh and then discarded, to avoid the error oc-

curring again when that byte is internally moved.

This bit is automatically cleared when bit FEERR

of the FESR0 register is cleared by software.

Bits 4:0 = Reserved.

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