ST92T163R4D0 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST92T163R4D0

8/16-BIT FULL SPEED USB MCU FOR COMPOSITE DEVICES WITH 16 ENDPOINTS, 20K ROM, 2K RAM, I2C, SCI, & MFT

STMicroelectronics 

ST92163 - MULTIFUNCTION TIMER (MFT)

MULTIFUNCTION TIMER (Cont’d)

INTERRUPT/DMA MASK REGISTER (IDMR)

R255 - Read/Write

Register Page: 10

Reset value: 0000 0000 (00h)

7

0

GT-

IEN

CP0D CP0I

CP1I

CM0

D

CM0I

CM1I

OUI

Bit 7 = GTIEN: Global timer interrupt enable.

This bit is set and cleared by software.

0: Disable all Timer interrupts

1: Enable all timer Timer Interrupts from enabled

sources

Bit 6 = CP0D: Capture 0 DMA mask.

This bit is set by software to enable a Capt0 DMA

transfer and cleared by hardware at the end of the

block transfer.

0: Disable capture on REG0R DMA

1: Enable capture on REG0R DMA

Bit 5 = CP0I: Capture 0 interrupt mask.

0: Disable capture on REG0R interrupt

1: Enable capture on REG0R interrupt (or Capt0

DMA End of Block interrupt if CP0D=1)

Bit 4 = CP1I: Capture 1 interrupt mask.

This bit is set and cleared by software.

0: Disable capture on REG1R interrupt

1: Enable capture on REG1R interrupt

Bit 3 = CM0D: Compare 0 DMA mask.

This bit is set by software to enable a Comp0 DMA

transfer and cleared by hardware at the end of the

block transfer.

0: Disable compare on CMP0R DMA

1: Enable compare on CMP0R DMA

Bit 2 = CM0I: Compare 0 Interrupt mask.

This bit is set and cleared by software.

0: Disable compare on CMP0R interrupt

1: Enable compare on CMP0R interrupt (or

Comp0 DMA End of Block interrupt if CM0D=1)

Bit 1 = CM1I: Compare 1 Interrupt mask.

This bit is set and cleared by software.

0: Disable compare on CMP1R interrupt

1: Enable compare on CMP1R interrupt

Bit 0 = OUI:

Overflow/Underflow interrupt mask.

This bit is set and cleared by software.

0: Disable Overflow/Underflow interrupt

1: Enable Overflow/Underflow interrupt

DMA COUNTER POINTER REGISTER (DCPR)

R240 - Read/Write

Register Page: 9

Reset value: undefined

7

0

DCP7

DCP6

DCP5

DCP4

DCP3

DCP2

DMA

SRCE

REG/

MEM

Bit 7:2 = DCP[7:2]: MSBs of DMA counter register

address.

These are the most significant bits of the DMA

counter register address programmable by soft-

ware. The DCP2 bit may also be toggled by hard-

ware if the Timer DMA section for the Compare 0

channel is configured in Swap mode.

Bit 1 = DMA-SRCE: DMA source selection.

This bit is set and cleared by hardware.

0: DMA source is a Capture on REG0R register

1: DMA destination is a Compare on CMP0R reg-

ister

Bit 0 = REG/MEM: DMA area selection.

This bit is set and cleared by software. It selects

the source and destination of the DMA area

0: DMA from/to memory

1: DMA from/to Register File

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