ST92T163R4D0 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST92T163R4D0

8/16-BIT FULL SPEED USB MCU FOR COMPOSITE DEVICES WITH 16 ENDPOINTS, 20K ROM, 2K RAM, I2C, SCI, & MFT

STMicroelectronics 

ST92163 - USB PERIPHERAL (USB)

USB INTERFACE (Cont’d)

Bit 4 = ESUSP: End Suspend mode.

0: No activity detected during Suspend mode

1: USB activity is detected that wakes up the USB

interface during suspend mode.

Note: This event asynchronously clears the

LP_SUSP bit in the USBCTLR register and acti-

vates the WKUP15 internal wake-up line to notify

the WUIMU (if STOP_CK_EN=1 in the

DEVCONF1 register)

Bit 3 = SUSP Suspend mode request.

0: No Suspend mode request

1: No USB traffic has been received for 3 ms.

Note: The suspend condition check is enabled im-

mediately after any USB reset and is disabled by

hardware when suspend mode is active

(LP_SUSP = 1) until the end of resume sequence.

Bit 2 = RESET: USB Reset request.

0: No USB Reset received.

1: USB Reset received.

Note: Device address and endpoint registers are

reset by an USB reset.

Bit 1 = SOF: Start Of Frame.

0: No SOF packet received.

1: SOF packet received.

Bit 0 = ESOF: Expected Start Of Frame.

0: No SOF packet missed

1: SOF packet is expected but not received.

INTERRUPT MASK REGISTER (USBIMR)

R250 - Read/Write

Register page: 15

Reset Value: 0000 0000 (00h)

7

0

DOVR ERR ESUSP SUSP RESET SOF ESOF

0

M

M

M

M

M

M

M

This register contains mask bits for all interrupt

condition bits included in the USBISTR register.

Whenever one of the USBIMR bits is 1, if the cor-

responding USBISTR bit is 1, an interrupt request

is generated. For an explanation of each bit, refer

to the USBISTR register description.

INTERRUPT PRIORITY REGISTER (USBIPR)

R251- Read/Write

Register page: 15

Reset Value: 0xxx 0xxx (xxh)

7

0

IE E

PIECE PIECE PIECE

2

1

0

NIEE

PNIEN PNIEN PNIEN

2

1

0

Bit 7 = IEE: Isochronous Endpoint Enable.

Set by software to enable Isochronous Endpoints.

This also enables CTR interrupts related to iso-

chronous endpoints and DMA overrun interrupts.

0: Isochronous endpoints disabled

1: Isochronous endpoints enabled

Bits 6:4 = PIECE[2:0]: Priority level on Iso-

chronous Endpoint and DMA Over/Underrun.

Set by software to define the priority level of the is-

ochronous endpoint CTR events (0 is the highest

priority).

Bit 3 = NIEE: Non-Isochronous Endpoint Enable.

Set by software to enable Non-Isochronous End-

points. This also enables CTR interrupts related to

non-isochronous (bulk, control, interrupt) end-

points.

0: Non-Isochronous endpoints disabled

1: Non-Isochronous endpoints enabled

Bits 2:0 = PNIEN[2:0]: Priority level of Non Iso-

chronous Endpoints and Notification.

Set by software to define the priority level of non-

isochronous endpoint (bulk, control, interrupt)

CTR events. 0 is the highest priority.

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