PSD934210MT View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
PSD934210MT
STMicroelectronics
PSD934210MT Datasheet PDF : 89 Pages
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PSD834F2V
Table 18. Port Operating Modes
Port Mode
Port A
MCU I/O
Yes
PLD I/O
McellAB Outputs
Yes
McellBC Outputs
No
Additional Ext. CS Outputs No
PLD Inputs
Yes
Address Out
Yes (A7 – 0)
Address In
Yes
Data Port
Yes (D7 – 0)
Peripheral I/O
Yes
JTAG ISP
No
Note: 1. Can be multiplexed with other I/O functions.
Port B
Yes
Yes
Yes
No
Yes
Yes (A7 – 0)
or (A15 – 8)
Yes
No
No
No
Port C
Yes
No
Yes
No
Yes
No
Yes
No
No
Yes1
Port D
Yes
No
No
Yes
Yes
No
Yes
No
No
No
Table 19. Port Operating Mode Settings
Mode
Defined in
PSDabel
Defined in PSD
Configuration
Control
Register
Setting
Direction
Register
Setting
VM
Register
Setting
JTAG Enable
MCU I/O
Declare pins only N/A1
1 = output,
0
0 = input N/A
N/A
(Note 2)
PLD I/O
Logic equations N/A
N/A
(Note 2) N/A
N/A
Data Port (Port A) N/A
Specify bus type N/A
N/A
N/A
N/A
Address Out
(Port A,B)
Declare pins only N/A
1
1 (Note 2) N/A
N/A
Address In
(Port A,B,C,D)
Logic for equation
Input Macrocells
N/A
N/A
N/A
N/A
N/A
Peripheral I/O
(Port A)
Logic equations
(PSEL0 & 1)
N/A
N/A
N/A
PIO bit = 1 N/A
JTAG ISP (Note 3) JTAGSEL
JTAG
Configuration
N/A
N/A
N/A
JTAG_Enable
Note: 1. N/A = Not Applicable
2. The direction of the Port A,B,C, and D pins are controlled by the Direction Register ORed with the individual output enable product
term (.oe) from the CPLD AND Array.
3. Any of these three methods enables the JTAG pins on Port C.
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