STG3005A2STR View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
STG3005A2STR Datasheet PDF : 85 Pages
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RIVA128ZX
128-BIT 3D MULTIMEDIA ACCELERATOR
5.2 PCI TIMING SPECIFICATION
The timing specification of the PCI interface takes the form of generic setup, hold and delay times of tran-
sitions to and from the rising edge of PCICLK as shown in Figure 17.
Figure 17. PCI timing parameters
PCICLK
Output timing parameters Output delay
Tri-state output
tVAL
tON
tOFF
Input timing parameters
PCICLK
Input
tSU
tH
Table 6. PCI timing parameters
Symbol
tVAL
tVAL(PTP)
tON
tOFF
tSU
tSU(PTP)
tSU(PTP)
tH
Parameter
PCICLK to signal valid delay (bussed signals)
PCICLK to signal valid delay (point to point)
Float to active delay
Active to float delay
Input set up time to PCICLK (bussed signals)
Input set up time to PCICLK (PCIGNT#)
Input set up time to PCICLK (PCIREQ#)
Input hold time from PCICLK
Min.
2
2
2
7
10
12
0
Max.
11
12
28
Unit
Notes
ns
1
ns
1
ns
ns
ns
1
ns
1
ns
ns
NOTE
1 PCIREQ# and PCIGNT# are point to point signals and have different valid delay and input setup times than bussed sig-
nals. All other signals are bussed.
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