C164CL/SL View Datasheet(PDF) - Infineon Technologies

Part Name

Description

Manufacturer

C164CL/SL

16-Bit Single-Chip Microcontroller

Infineon Technologies 

C164CI/SI

C164CL/SL

AC Characteristics

Definition of Internal Timing

The internal operation of the C164CI is controlled by the internal CPU clock fCPU. Both

edges of the CPU clock can trigger internal (e.g. pipeline) or external (e.g. bus cycles)

operations.

The specification of the external timing (AC Characteristics) therefore depends on the

time between two consecutive edges of the CPU clock, called “TCL” (see Figure 11).

Phase Locked Loop Operation

fOSC

TCL

fCPU

Direct Clock Drive

fOSC

TCL

TCL

fCPU

TCL

Prescaler Operation

fOSC

fCPU

TCL

TCL

MCT04338

Figure 11 Generation Mechanisms for the CPU Clock

The CPU clock signal fCPU can be generated from the oscillator clock signal fOSC via

different mechanisms. The duration of TCLs and their variation (and also the derived

external timing) depends on the used mechanism to generate fCPU. This influence must

be regarded when calculating the timings for the C164CI.

Note: The example for PLL operation shown in Figure 11 refers to a PLL factor of 4.

The used mechanism to generate the basic CPU clock is selected by bitfield CLKCFG

in register RP0H.7-5.

Upon a long hardware reset register RP0H is loaded with the logic levels present on the

upper half of PORT0 (P0H), i.e. bitfield CLKCFG represents the logic levels on pins

Data Sheet

50

V2.0, 2001-05

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