ATSAM4LS4BA-AU View Datasheet(PDF) - Atmel Corporation

Part Name

Description

Manufacturer

ATSAM4LS4BA-AU

ATSAM ARM-based Flash MCU

Atmel Corporation 

ATSAM4L8/L4/L2

8.9 System Manager Access Port (SMAP)

Rev.: 1.0.0.0

8.9.1 Features

• Chip Erase command and status

• Cortex-M4 core reset source

• 32-bit Cyclic Redundancy check of any memory accessible through the bus matrix

• Unlimited Flash User page read access

• Chip identification register

8.9.2

Overview

The SMAP provides memory-related services and also Cortex-M4 core reset control to a debug-

ger through the Debug Port. This makes possible to halt the CPU and program the device after

reset.

8.9.3 Block Diagram

Figure 8-7. SMAP Block Diagram

SMAP

Ahb_Master

AHB

System

Bus Matrix

DAP Bus

DAP

Interface

Core

AHB

chip_erase

Flash

Controller

SMAP Core reset request

PM

Reset

Controller

Cortex-M4 core reset

System reset

8.9.4

Initializing the Module

The SMAP can be accessed only if the CPU clock is running and the SWJ-DP has been acti-

vated by issuing a CDBGPWRUP request. For more details, refer to the ARM Debug Interface

v5.1 Architecture Specification.

Then it must be enabled by writing a one to the EN bit of the CR register (CR.EN) before writing

or reading other registers. If the SMAP is not enabled it will discard any read or write operation.

8.9.5

Stopping the Module

To stop the module, the user must write a one to the DIS bit of the CR register (CR.DIS). All the

user interface and internal registers will be cleared and the internal clock will be stopped.

78

42023GS–SAM–03/2014

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