SI3016-F-FS View Datasheet(PDF) - Silicon Laboratories

Part Name

Description

Manufacturer

SI3016-F-FS

3.3 V ENHANCED GLOBAL DIRECT ACCESS ARRANGEMENT

Silicon Laboratories 

LVCS[4:0] bits indicate the amount of loop current

flowing. If the FDT fails to be set following an off-hook

request, the PDL bit in Register 6 must be set high for at

least 1 ms to reset the line side.

Another useful bit is the communication link error (CLE)

bit. The CLE bit indicates a timeout error for the

isolation link. This condition indicates a severe error in

programming or possibly a defective line-side chip.

4.27. Revision Identification

The Si3016 provides the system designer the ability to

determine the revision of the system-side module and/

or the Si3016. The REVA[3:0] bits identify the revision of

the system-side module. The REVB[3:0] and CBID bits

identify the revision of the Si3016. Table 12 lists revision

values for both chips.

Table 12. Revision Values

Revision

C

D

E

F

System-Side

Module

1010

—

—

—

Si3016

—

1100

1101

1110

Si3016

Rev. 1.0

25

Share Link: