Si3016
Register 11. Chip A Revision
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
REVA[3:0]
Type
R
Reset settings = N/A
Bit Name
Function
7:4 Reserved Read returns zero.
3:0 REVA[3:0] Chip A Revision.
Four-bit value indicating the revision of the integrated system-side module.
Register 12. Line Side Status
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
CLE
FDT
LCS[3:0]
Type
R/W
R
R
Reset settings = N/A
Bit Name
Function
7
CLE Communications (isolation link) Error.
0 = Communication link between the integrated system-side module and Si3016 is operating
correctly.
1 = Indicates a communication problem between the integrated system-side module and the
Si3016. When it goes high, it remains high until a logic 0 is written to it.
6
FDT Frame Detect.
0 = Indicates link has not established frame lock.
1 = Indicates link frame lock has been established.
5:4 Reserved Read returns zero.
3:0 LCS[3:0] Loop Current Sense.
Four-bit value returning the loop current. It is decoded from the LVCS bits. See LVCS bits for
line voltage and current monitoring. When off-hook, these bits are decoded as follows from
LVCS[4:0]:
LCS[3:0] = LVCS[4:1] except
when LVCS[4:0] = 11110, LCS[3:0] = 1110 or
when LVCS[4:0] = 00001, LCS[3:0] = 0001.
When on-hook, LCS[3:0] = LVCS[4:1].
32
Rev. 1.0