SI3201-FS View Datasheet(PDF) - Silicon Laboratories

Part Name

Description

Manufacturer

SI3201-FS

PROSLIC® PROGRAMMABLE CMOS SLIC WITH RINGING/BATTERY VOLTAGE GENERATION

Silicon Laboratories 

Si3230

amplitude, where rise time and period are related

through the following equation for the crest factor of a

trapezoidal waveform.

tRISE

=

3--

4

T

⎛

⎝

1

–

-C---1-F----2-⎠⎞

where T = ringing period, and CF = desired crest factor.

For example, to generate a 71 VPK, 20 Hz ringing

signal, the equations are as follows:

RNGY(20 Hz) = 12-- × -2---0---1--H-----z- × 8000 = 200 = C8h

RNGX(71 VPK) = 79----16-- × 215= 24235 = 5EABh

For a crest factor of 1.3 and a period of 0.05 seconds

(20 Hz), the rise time requirement is 0.0153 seconds.

RCO(20 Hz, 1.3 crest factor)

= 0----.--02---1--×-5----32---4-×---2--8-3--0-5---0---0--= 396= 018Ch

In addition, the user must select the trapezoidal ringing

waveform by writing TSWS = 1 in direct Register 34.

2.4.4. Ringing DC voltage Offset

A dc offset can be added to the ac ringing waveform by

defining the offset voltage in ROFF (indirect

Register 19). The offset, VROFF, is added to the ringing

signal when RVO is set to 1 (direct Register 34, bit 1).

The value of ROFF is calculated as follows:

ROFF

=

-V----R---O----F----F- × 215

96

2.4.5. Linefeed Considerations During Ringing

Care must be taken to keep the generated ringing signal

within the ringing voltage rails (GNDA and VBAT) to

maintains proper biasing of the external bipolar

transistors. If the ringing signal nears the rails, a

distorted ringing signal and excessive power dissipation

in the external transistors will result.

To prevent this invalid operation, set the VBATH value

(direct Register 74) to a value higher than the maximum

peak ringing voltage. The discussion below outlines the

considerations and equations that govern the selection

of the VBATH setting for a particular desired peak

ringing voltage.

First, the required amount of ringing overhead voltage,

VOVR, is calculated based on the maximum value of

current through the load, ILOAD,PK, the minimum current

gain of Q5 and Q6, and a reasonable voltage required

to keep Q5 and Q6 out of saturation. For ringing signals

up to VPK = 87 V, VOVR = 7.5 V is a safe value.

However, to determine VOVR for a specific case, use the

equations below.

ILOAD,PK

=

V-----A---C----,-P----K-

RLOAD

+

IOS

=

VAC,PK × 6--N--.-9--R---E-k---NΩ--- + IOS

where:

NREN is the ringing REN load (max value = 5),

IOS is the offset current flowing in the line driver circuit

(max value = 2 mA), and

VAC,PK = amplitude of the ac ringing waveform.

It is good practice to provide a buffer of a few more

milliamperes for ILOAD,PK to account for possible line

leakages, etc. The total ILOAD,PK current should be

smaller than 80 mA.

VOVR

=

ILOAD,PK

×

-β----+-----1--

β

×

(80.6

Ω+1

V)

where β is the minimum expected current gain of

transistors Q5 and Q6.

The minimum value for VBATH is therefore given by the

following:

VBATH = VAC,PK + VROFF + VOVR

The ProSLIC is designed to create a fully balanced

ringing waveform, meaning that the TIP and RING

common mode voltage, (VTIP + VRING)/2, is fixed. This

voltage is referred to as VCM_RING and is

automatically set to the following:

VCM_RING

=

V-----B----A-----T----H-----–-----V----C-----M-----R---

2

VCMR is an indirect register which provides the

headroom by the ringing waveform with respect to the

VBATH rail. The value is set as a 4-bit setting in indirect

Register 40 with an LSB voltage of 1.5 V/LSB.

Register 40 should be set with the calculated VOVR to

provide voltage headroom during ringing.

Silicon revisions C and higher support the option to

briefly increase the maximum differential current limit

between the voltage transition of TIP and RING from

ringing to a dc linefeed state. This mode is enabled by

setting ILIMEN = 1 (direct Register 108, bit 7).

2.4.6. Ring Trip Detection

A ring trip event signals that the terminal equipment has

gone off-hook during the ringing state. The ProSLIC

performs ring trip detection digitally using its on-chip

monitor A/D converter. The functional blocks required to

implement ring trip detection is shown in Figure 14. The

primary input to the system is the Loop Current Sense

value provided by the current monitoring circuitry and

reported in direct Register 79. LCS data is processed by

the input signal processor when the ProSLIC is in the

Preliminary Rev. 0.96

31

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