Si3230
Table 22. Associated Power Monitoring and Power Fault Registers
Parameter
Description/
Range
Resolution
Register
Bits
Location*
Power Monitor Pointer
0 to 5 points to Q1
n/a
to Q6, respectively
PWRMP[2:0] Direct Register 76
Line Power Monitor Output
0 to 7.8 W for Q1,
Q2, Q5, Q6
0 to 0.9 W for Q3,
Q4
30.4 mW
3.62 mW
PWROM[7:0] Direct Register 77
Power Alarm Threshold, Q1 & Q2
0 to 7.8 W
30.4 mW
PPT12[7:0] Indirect Register 32
Power Alarm Threshold, Q3 & Q4
0 to 0.9 W
3.62 mW
PPT34[7:0] Indirect Register 33
Power Alarm Threshold, Q5 & Q6
0 to 7.8 W
30.4 mW
PPT56[7:0] Indirect Register 34
Thermal LPF Pole, Q1 & Q2
see equation above
NQ12[7:0] Indirect Register 37
Thermal LPF Pole, Q3 & Q4
see equation above
NQ34[7:0] Indirect Register 38
Thermal LPF Pole, Q5 & Q6
see equation above
NQ56[7:0] Indirect Register 39
Power Alarm Interrupt Pending
Bits 2 to 7 corre-
spond to Q1 to Q6,
respectively
n/a
QnAP[n+1], Direct Register 19
where n = 1 to 6
Power Alarm Interrupt Enable
Bits 2 to 7 corre-
spond to Q1 to Q6,
respectively
n/a
QnAE[n+1], Direct Register 22
where n = 1 to 6
Power Alarm
0 = manual mode
n/a
Automatic/Manual Detect
1 = enter open state
upon power alarm
AOPN
Direct Register 67
*Note: The ProSLIC uses registers that are both directly and indirectly mapped. A “direct” register is one that is mapped
directly. An “indirect” register is one that is accessed using the indirect access registers (direct registers 28 through
31).
Preliminary Rev. 0.96
21