SI3201-FS View Datasheet(PDF) - Silicon Laboratories

Part Name

Description

Manufacturer

SI3201-FS

PROSLIC® PROGRAMMABLE CMOS SLIC WITH RINGING/BATTERY VOLTAGE GENERATION

Silicon Laboratories 

Si3230

LCS

LVS

Input

Signal

ISP_OUT

Processor

Digital

LPF

+

–

LFS LCVE

NCLR

HYSTEN

Loop Closure

Threshold

Debounce

Filter

LCR

Interrupt

Logic

LCIP

LCDI

LCIE

LCRT LCRTL

Figure 9. Loop Closure Detection

2.1.6. Loop Closure Detection

2.1.8. Voltage-Based Loop Closure Detection

A loop closure event signals that the terminal equipment

has gone off-hook during on-hook transmission or on-

hook active states. The ProSLIC performs loop closure

detection digitally using its on-chip monitor A/D

converter. The functional blocks required to implement

loop closure detection are shown in Figure 9. The

primary input to the system is the Loop Current Sense

value provided in the LCS register (direct Register 79).

The LCS value is processed in the Input Signal

Processor when the ProSLIC is in the on-hook

transmission or on-hook active linefeed state, as

indicated by the Linefeed Shadow register, LFS[2:0]

(direct Register 64). The data then feeds into a

programmable digital low-pass filter, which removes

unwanted ac signal components before threshold

detection.

The output of the low-pass filter is compared to a

programmable threshold, LCRT (indirect register 28).

The threshold comparator output feeds a programmable

debouncing filter. The output of the debouncing filter

remains in its present state unless the input remains in

the opposite state for the entire period of time

programmed by the loop closure debounce interval,

LCDI (direct Register 69). If the debounce interval has

been satisfied, the LCR bit will be set to indicate that a

valid loop closure has occurred. A loop closure interrupt

is generated if enabled by the LCIE bit (direct

Register 22). Table 23 lists the registers that must be

written or monitored to correctly detect a loop closure

condition.

2.1.7. Loop Closure Threshold Hysteresis

Programmable hysteresis to the loop closure threshold

can be enabled by setting HYSTEN = 1 (direct

Register 108, bit 0). The hysteresis is defined by LCRT

(indirect Register 28) and LCRTL (indirect Register 43),

which set the upper and lower bounds, respectively.

Optional voltage-based loop closure detection mode is

enabled by setting LCVE = 1 (direct Register 108,

bit 2). In this mode, the loop voltage is compared to the

loop closure threshold register (LCRT), which

represents a minimum voltage threshold instead of a

maximum current threshold. If hysteresis is also

enabled, LCRT represents the upper voltage boundary,

and LCRTL represents the lower voltage boundary for

hysteresis. Although voltage-based loop closure

detection is an option, the default current-based loop

closure detection is recommended.

Table 23. Register Set for Loop

Closure Detection

Parameter

Loop Closure

Interrupt Pending

Loop Closure

Interrupt Enable

Loop Closure Threshold

Loop Closure

Threshold—Lower

Loop Closure Filter

Coefficient

Loop Closure Detect

Status (monitor only)

Loop Closure Detect

Debounce Interval

Hysteresis Enable

Voltage-Based Loop

Closure

Register

LCIP

LCIE

LCRT[5:0]

LCRTL[5:0]

NCLR[12:0]

LCR

LCDI[6:0]

HYSTEN

LCVE

Location

Direct Reg. 19

Direct Reg. 22

Indirect Reg. 28

Indirect Reg. 43

Indirect Reg. 35

Direct Reg. 68

Direct Reg. 69

Direct Reg. 108

Direct Reg. 108

22

Preliminary Rev. 0.96

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