Si3230
Table 30. Direct Register Summary (Continued)
Register Name
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3
Bit 2
Bit 1 Bit 0
94 PWM Pulse Width
DCPW[7:0]
95 Reserved
96 Calibration Control/
Status Register 1
CAL CALSP CALR CALT CALD CALC CALIL
97 Calibration Control/
Status Register 2
CALM1 CALM2 CALDAC CALADC CALCM
98 RING Gain Mismatch
Calibration Result
CALGMR[R4:0]
99 TIP Gain Mismatch
Calibration Result
CALGMT[4:0]
100 Differential Loop
Current Gain
Calibration Result
CALGD[4:0]
101 Common Mode Loop
Current Gain
Calibration Result
CALGC[4:0]
102 Current Limit
Calibration Result
CALGIL[3:0]
103 Monitor ADC Offset
Calibration Result
CALMG1[3:0]
CALMG2[3:0]
104 Analog DAC/ADC Offset
DACP DACN ADCP ADCN
105 DAC Offset Calibration
Result
DACOF[7:0]
106 Common Mode Balance
Calibration Result
CMBAL[5:0]
107 DC Peak Voltage
Calibration Result
CMDCPK[3:0]
108 Enhancement Enable ILIMEN FSKEN DCEN ZSEXT SWDB LCVE DCFIL HYSTEN
Preliminary Rev. 0.96
43