SI3201-X-FS View Datasheet(PDF) - Silicon Laboratories

Part Name

Description

Manufacturer

SI3201-X-FS

PROSLIC® PROGRAMMABLE CMOS SLIC WITH RINGING/BATTERY VOLTAGE GENERATION

Silicon Laboratories 

Si3233

2.2.8. Voltage-Based Loop Closure Detection

An optional voltage-based loop closure detection mode

is enabled by setting LCVE = 1 (direct Register 108,

bit 2). In this mode, the loop voltage is compared to the

loop closure threshold register (LCRT), which

represents a minimum voltage threshold instead of a

maximum current threshold. If hysteresis is also

enabled, LCRT represents the upper voltage boundary,

and LCRTL represents the lower voltage boundary for

hysteresis. Although voltage-based loop closure

detection is an option, the default current-based loop

closure detection is recommended.

Table 23. Register Set for Loop

Closure Detection

Parameter

Loop Closure

Interrupt Pending

Loop Closure

Interrupt Enable

Loop Closure Threshold

Loop Closure

Threshold—Lower

Loop Closure Filter

Coefficient

Loop Closure Detect

Status (monitor only)

Loop Closure Detect

Debounce Interval

Hysteresis Enable

Voltage-Based Loop

Closure

Register

LCIP

LCIE

LCRT[5:0]

LCRTL[5:0]

NCLR[12:0]

LCR

LCDI[6:0]

HYSTEN

LCVE

Location

Direct Reg. 19

Direct Reg. 22

Indirect Reg. 15

Indirect Reg. 66

Indirect Reg. 22

Direct Reg. 68

Direct Reg. 69

Direct Reg. 108

Direct Reg. 108

2.2.9. Linefeed Calibration

An internal calibration algorithm corrects for internal and

external component errors. The calibration is initiated by

setting the CAL bit in direct Register 96. Upon

completion of the calibration cycle, this bit is

automatically reset.

It is recommended that a calibration be executed

following system power-up. Upon release of the chip

reset, the Si3233 will be in the open state. After

powering up the dc-dc converter and allowing it to settle

for time (tsettle) the calibration can be initiated.

Additional calibrations may be performed, but only one

calibration should be necessary as long as the system

remains powered up.

During calibration, VBAT, VTIP, and VRING voltages are

controlled by the calibration engine to provide the

correct external voltage conditions for the algorithm.

Calibration should be performed in the on-hook state.

RING or TIP must not be connected to ground during

the calibration.

2.3. Battery Voltage Generation and

Switching

The Si3233 integrates a dc-dc converter controller that

dynamically regulates a single output voltage. This

eliminates the need to supply large external battery

voltages. Instead, it converts a single positive input

voltage into the real-time battery voltage needed for any

given state according to programmed linefeed

parameters.

2.3.1. DC-DC Converter General Description

The dc-dc converter dynamically generates the large

negative voltages required to operate the linefeed

interface. The Si3233 acts as the controller for a buck-

boost dc-dc converter that converts a positive dc

voltage into the desired negative battery voltage. In

addition to eliminating external power supplies, this

allows the Si3233 to dynamically control the battery

voltage to the minimum required for any given mode of

operation.

Extensive design guidance can be obtained from

Application Note 45 (AN45) and from an interactive dc-

dc converter design spreadsheet. Both of these

documents are available on the Silicon Laboratories

website (www.silabs.com).

2.3.2. BJT/Inductor Circuit Using Si3233

The BJT/Inductor circuit, as defined in Figure 4, offers a

flexible, low-cost solution. Depending on selected L1

inductance value and the switching frequency, the input

voltage (VDC) can range from 5 V to 30 V. By nature of a

dc-dc converter’s operation, peak and average input

currents can become large with small input voltages.

Consider this when selecting the appropriate input

voltage and power rating for the VDC power supply.

In this circuit, a PNP power BJT (Q7) switches the

current flow through low ESR inductor L1. The Si3233

uses the DCDRV and DCFF pins to switch Q7 on and

off. DCDRV controls Q7 through NPN BJT Q8. DCFF is

ac coupled to Q7 through capacitor C10 to assist R16 in

turning off Q7. Therefore, DCFF must have opposite

polarity to DCDRV, and the Si3233 (not Si3233M) must

be used.

2.3.3. MOSFET/Transformer Circuit Option Using

Si3233M

The MOSFET/transformer circuit option, as defined in

Figure 5, offers higher power efficiencies across a larger

input voltage range. Depending on the transformer’s

primary inductor value and the switching frequency, the

input voltage (VDC) can range from 3.3 V to 35 V.

Therefore, it is possible to power the entire ProSLIC

Preliminary Rev. 0.5

23

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