Si3233
Register 10. Two-Wire Impedance Synthesis Control
Bit
D7
D6
Name
Type
Reset settings = 0000_1000
D5
D4
CLC[1:0]
R/W
D3
TISE
R/W
D2
D1
D0
TISS[2:0]
R/W
Bit
Name
Function
7:6 Reserved Read returns zero.
5:4
CLC[1:0] Line Capacitance Compensation.
00 = Off
01 = 4.7 nF
10 = 10 nF
11 = Reserved
3
TISE
Two-Wire Impedance Synthesis Enable.
0 = Two-wire impedance synthesis disabled.
1 = Two-wire impedance synthesis enabled.
2:0
TISS[2:0] Two-Wire Impedance Synthesis Selection.
000 = 600 Ω
001 = 900 Ω
010 = Japan (600 Ω + 1 µF); requires RZREF = 12 kΩ and
C3, C4 = 100 nF
011 = 900 Ω + 2.16 µF; requires RZREF = 18 kΩ and
C3, C4 = 220 nF
100 = CTR21 270 Ω + (750 Ω || 150 nF)
101 = Australia/New Zealand 220 Ω + (820 Ω || 120 nF)
110 = Slovakia/Slovenia/South Africa 220 Ω + (820 Ω || 115 nF)
111 = China 200 Ω + (680 Ω || 100 nF)
44
Preliminary Rev. 0.5