5. Pin Descriptions: Si3233
NC 1 38 37 36 35 34 33 32 31
FSYNC 2
30
RESET 3
29
SDCH 4
28
SDCL 5
27
VDDA1 6
26
IREF 7
25
CAPP 8
24
QGND 9
23
CAPM 10
22
STIPDC 11
21
SRINGDC 12 13 14 15 16 17 18 19 20
SDITHRU
DCDRV
DCFF
TEST1
GNDD
VDDD
ITIPN
ITIPP
VDDA2
IRINGP
IRINGN
IGMP
Si3233
Pin #
35
36
37
38
1
2
3
4
5
6
7
Name
Description
CS
INT
PCLK
TEST2
NC
FSYNC
RESET
SDCH
SDCL
VDDA1
IREF
Chip Select.
Active low. When inactive, SCLK and SDI are ignored and SDO is high impedance. When
active, the serial port is operational.
Interrupt.
Maskable interrupt output. Open drain output for wire-ORed operation.
PCM Bus Clock.
Clock input.
Test.
Enables test modes for Silicon Labs internal testing. This pin should always be tied to
ground for normal operation.
No Connect.
Frame Synch.
8 kHz frame synchronization signal for the PCM bus. May be short or long pulse format.
Reset.
Active low input. Hardware reset used to place all control registers in the default state.
DC Monitor.
DC-DC converter monitor input used to detect overcurrent situations in the converter.
DC Monitor.
DC-DC converter monitor input used to detect overcurrent situations in the converter.
Analog Supply Voltage.
Analog power supply for internal analog circuitry.
Current Reference.
Connects to an external resistor used to provide a high accuracy reference current.
Preliminary Rev. 0.5
91