16 Mbit Concurrent SuperFlash + 2/4 Mbit SRAM ComboMemory
SST34HF1621C / SST34HF1641C
Data Sheet
ADDRESSES AMSS3-0
WE#
TWCS
TWPS
TBWS
TWRS
BES1#
BES2
TBWS
TAWS
TASTS
TBYWS
UBS#, LBS#
TDSS
TDHS
DQ15-8, DQ7-0
NOTE 2
VALID DATA IN
NOTE 2
1252 F06.0
Note: 1. If OE# is High during the Write cycle, the outputs will remain at high impedance.
2. Because DIN signals may be in the output state at this time, input signals of reverse polarity must not be applied.
3. AMSS = Most Significant SRAM Address
AMSS = A16 for SST34HF1621C and A17 for SST34HF1641C
FIGURE 8: SRAM Write Cycle Timing Diagram (UBS#, LBS# Controlled)1 x16 SRAM ONLY
©2006 Silicon Storage Technology, Inc.
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