Data Sheet
ADDRESS A19-0
BEF#
OE#
WE#
DQ15-0
16 Mbit Concurrent SuperFlash + 2/4 Mbit SRAM ComboMemory
SST34HF1621C / SST34HF1641C
VIH
HIGH-Z
TRC
TAA
TCE
TOE
TOLZ
TCLZ
TOH
DATA VALID
TOHZ
TCHZ
DATA VALID
HIGH-Z
1252 F07.0
FIGURE 9: Flash Read Cycle Timing Diagram for Word Mode
(For Byte Mode A-1 = Address Input)
TBP
ADDRESS A19-0
WE#
OE#
555
TAH
TWP
2AA
TAS
TWPH
555
ADDR
TCH
BEF#
TCS?
TBY
TBR
RY/BY#
TDS
DQ15-0
TDH
XXAA XX55 XXA0
DATA
WORD
(ADDR/DATA)
Note: X can be VIL or VIH, but no other value.
FIGURE 10: Flash WE# Controlled Program Cycle Timing Diagram for Word Mode
(For Byte Mode A-1 = Address Input)
VALID
1252 F08.1
©2006 Silicon Storage Technology, Inc.
22
S71252-03-000
8/06