PIC16C73T-04I/SO View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC16C73T-04I/SO

8-Bit CMOS Microcontrollers with A/D Converter

Microchip Technology 

PIC16C7X

FIGURE 10-1: CCP1CON REGISTER (ADDRESS 17h)/CCP2CON REGISTER (ADDRESS 1Dh)

U-0

—

bit7

U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— CCPxX CCPxY CCPxM3 CCPxM2 CCPxM1 CCPxM0

bit0

bit 7-6: Unimplemented: Read as '0'

R = Readable bit

W = Writable bit

U = Unimplemented bit,

read as ‘0’

- n =Value at POR reset

bit 5-4: CCPxX:CCPxY: PWM Least Significant bits

Capture Mode: Unused

Compare Mode: Unused

PWM Mode: These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPRxL.

bit 3-0: CCPxM3:CCPxM0: CCPx Mode Select bits

0000 = Capture/Compare/PWM off (resets CCPx module)

0100 = Capture mode, every falling edge

0101 = Capture mode, every rising edge

0110 = Capture mode, every 4th rising edge

0111 = Capture mode, every 16th rising edge

1000 = Compare mode, set output on match (CCPxIF bit is set)

1001 = Compare mode, clear output on match (CCPxIF bit is set)

1010 = Compare mode, generate software interrupt on match (CCPxIF bit is set, CCPx pin is unaffected)

1011 = Compare mode, trigger special event (CCPxIF bit is set; CCP1 resets TMR1; CCP2 resets TMR1

and starts an A/D conversion (if A/D module is enabled))

11xx = PWM mode

10.1 Capture Mode

Applicable Devices

72 73 73A 74 74A 76 77

In Capture mode, CCPR1H:CCPR1L captures the

16-bit value of the TMR1 register when an event occurs

on pin RC2/CCP1. An event is defined as:

• Every falling edge

• Every rising edge

• Every 4th rising edge

• Every 16th rising edge

An event is selected by control bits CCP1M3:CCP1M0

(CCP1CON<3:0>). When a capture is made, the inter-

rupt request flag bit CCP1IF (PIR1<2>) is set. It must

be cleared in software. If another capture occurs before

the value in register CCPR1 is read, the old captured

value will be lost.

10.1.1 CCP PIN CONFIGURATION

In Capture mode, the RC2/CCP1 pin should be config-

ured as an input by setting the TRISC<2> bit.

Note:

If the RC2/CCP1 is configured as an out-

put, a write to the port can cause a capture

condition.

FIGURE 10-2: CAPTURE MODE

OPERATION BLOCK

DIAGRAM

RC2/CCP1

Pin

Set flag bit CCP1IF

Prescaler

(PIR1<2>)

÷ 1, 4, 16

CCPR1H

and

edge detect

Capture

Enable

TMR1H

CCP1CON<3:0>

Q’s

CCPR1L

TMR1L

10.1.2 TIMER1 MODE SELECTION

Timer1 must be running in timer mode or synchronized

counter mode for the CCP module to use the capture

feature. In asynchronous counter mode, the capture

operation may not work.

10.1.3 SOFTWARE INTERRUPT

When the Capture mode is changed, a false capture

interrupt may be generated. The user should keep bit

CCP1IE (PIE1<2>) clear to avoid false interrupts and

should clear the flag bit CCP1IF following any such

change in operating mode.

DS30390E-page 72

© 1997 Microchip Technology Inc.

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