PIC16C73T-04I/SO View Datasheet(PDF) - Microchip Technology
Part Name
Description
Manufacturer
PIC16C73T-04I/SO Datasheet PDF : 288 Pages
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PIC16C7X
Applicable Devices
72 73 73A 74 74A 76 77
11.2.1
OPERATION OF SSP MODULE IN SPI
MODE
Applicable Devices
72 73 73A 74 74A 76 77
The SPI mode allows 8-bits of data to be synchro-
nously transmitted and received simultaneously. To
accomplish communication, typically three pins are
used:
• Serial Data Out (SDO)
• Serial Data In (SDI)
• Serial Clock (SCK)
Additionally a fourth pin may be used when in a slave
mode of operation:
• Slave Select (SS)
When initializing the SPI, several options need to be
specified. This is done by programming the appropriate
control bits in the SSPCON register (SSPCON<5:0>).
These control bits allow the following to be specified:
• Master Mode (SCK is the clock output)
• Slave Mode (SCK is the clock input)
• Clock Polarity (Output/Input data on the Rising/
Falling edge of SCK)
• Clock Rate (Master mode only)
• Slave Select Mode (Slave mode only)
The SSP consists of a transmit/receive Shift Register
(SSPSR) and a Buffer register (SSPBUF). The SSPSR
shifts the data in and out of the device, MSb first. The
SSPBUF holds the data that was written to the SSPSR,
until the received data is ready. Once the 8-bits of data
have been received, that byte is moved to the SSPBUF
register. Then the Buffer Full bit, BF (SSPSTAT<0>)
and flag bit SSPIF are set. This double buffering of the
received data (SSPBUF) allows the next byte to start
reception before reading the data that was just
received. Any write to the SSPBUF register during
transmission/reception of data will be ignored, and the
write collision detect bit, WCOL (SSPCON<7>) will be
set. User software must clear bit WCOL so that it can
be determined if the following write(s) to the SSPBUF
completed successfully. When the application software
is expecting to receive valid data, the SSPBUF register
should be read before the next byte of data to transfer
is written to the SSPBUF register. The Buffer Full bit BF
(SSPSTAT<0>) indicates when the SSPBUF register
has been loaded with the received data (transmission
is complete). When the SSPBUF is read, bit BF is
cleared. This data may be irrelevant if the SPI is only a
transmitter. Generally the SSP Interrupt is used to
determine when the transmission/reception has com-
pleted. The SSPBUF register must be read and/or writ-
ten. If the interrupt method is not going to be used, then
software polling can be done to ensure that a write col-
lision does not occur. Example 11-1 shows the loading
of the SSPBUF (SSPSR) register for data transmission.
The shaded instruction is only required if the received
data is meaningful.
EXAMPLE 11-1: LOADING THE SSPBUF
(SSPSR) REGISTER
BSF STATUS, RP0 ;Specify Bank 1
LOOP BTFSS SSPSTAT, BF
;Has data been
;received
;(transmit
GOTO LOOP
;complete)?
;No
BCF STATUS, RP0
MOVF SSPBUF, W
;Specify Bank 0
;W reg = contents
MOVWF RXDATA
;of SSPBUF
;Save in user RAM
MOVF TXDATA, W
;W reg = contents
; of TXDATA
MOVWF SSPBUF
;New data to xmit
The block diagram of the SSP module, when in SPI
mode (Figure 11-3), shows that the SSPSR register is
not directly readable or writable, and can only be
accessed from addressing the SSPBUF register. Addi-
tionally, the SSP status register (SSPSTAT) indicates
the various status conditions.
FIGURE 11-3: SSP BLOCK DIAGRAM
(SPI MODE)
Read
Internal
data bus
Write
SSPBUF reg
RC4/SDI/SDA
RC5/SDO
SSPSR reg
bit0
shift
clock
RA5/SS/AN4
SS Control
Enable
Edge
Select
2
Clock Select
RC3/SCK/
SCL
SSPM3:SSPM0
4
Edge
Select
TMR2 output
2
Prescaler TCY
4, 16, 64
TRISC<3>
DS30390E-page 80
© 1997 Microchip Technology Inc.
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