ST72334N2B7(2003) View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
ST72334N2B7
(Rev.:2003)
(Rev.:2003)
STMicroelectronics
ST72334N2B7 Datasheet PDF : 153 Pages
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ST72334J/N, ST72314J/N, ST72124J
16.4 SUPPLY CURRENT CHARACTERISTICS
The following current consumption specified for
the ST7 functional operating modes over tempera-
ture range does not take into account the clock
source current consumption. To get the total de-
vice consumption, the two current values must be
added (except for HALT mode for which the clock
is stopped).
Symbol
∆IDD(∆Ta)
Parameter
Supply current variation vs. temperature
Conditions
Constant VDD and fCPU
Max Unit
10
%
16.4.1 RUN and SLOW Modes
Symbol
Parameter
Supply current in RUN mode 3)
(see Figure 63)
Supply current in SLOW mode 4)
(see Figure 64)
IDD
Supply current in RUN mode 3)
(see Figure 63)
Supply current in SLOW mode 4)
(see Figure 64)
Conditions
fOSC=2MHz, fCPU=1MHz
fOSC=4MHz, fCPU=2MHz
fOSC=8MHz, fCPU=4MHz
fOSC=16MHz, fCPU=8MHz
fOSC=2MHz, fCPU=62.5kHz
fOSC=4MHz, fCPU=125kHz
fOSC=8MHz, fCPU=250kHz
fOSC=16MHz, fCPU=500kHz
fOSC=2MHz, fCPU=1MHz
fOSC=4MHz, fCPU=2MHz
fOSC=8MHz, fCPU=4MHz
fOSC=16MHz, fCPU=8MHz
fOSC=2MHz, fCPU=62.5kHz
fOSC=4MHz, fCPU=125kHz
fOSC=8MHz, fCPU=250kHz
fOSC=16MHz, fCPU=500kHz
Typ 1)
1.2
2.1
3.9
7.4
0.4
0.5
0.7
1.0
0.3
0.8
1.6
3.5
0.1
0.2
0.3
0.5
Max 2)
1.8
3.5
7.0
14.0
0.9
1.1
1.4
2.0
1
1.5
3
7
0.3
0.5
0.6
1.0
Unit
mA
Figure 63. Typical IDD in RUN vs. fCPU
IDD [mA]
8
7
6
8MHz
4MHz
2MHz
1MHz
5
Figure 64. Typical IDD in SLOW vs. fCPU
IDD [mA]
1.2
500kHz
250kHz
125kHz
62.5kHz
1
0.8
4
0.6
3
0.4
2
0.2
1
0
3.2
3.5
4
4.5
5
5.5
0
3.2 3.5
4
4.5
5
5.5
VDD [V]
VDD [V]
Notes:
1. Typical data are based on TA=25°C, VDD=5V (4.5V≤VDD≤5.5V range) and VDD=3.4V (3.2V≤VDD≤3.6V range).
2. Data based on characterization results, tested in production at VDD max. and fCPU max.
3. CPU running with memory access, all I/O pins in input mode with a static value at VDD or VSS (no load), all peripherals
in reset state; clock input (OSC1) driven by external square wave, CSS and LVD disabled.
4. SLOW mode selected with fCPU based on fOSC divided by 32. All I/O pins in input mode with a static value at VDD or
VSS (no load), all peripherals in reset state; clock input (OSC1) driven by external square wave, CSS and LVD disabled.
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