ST72C314N4B7(2003) View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
ST72C314N4B7
(Rev.:2003)
(Rev.:2003)
STMicroelectronics
ST72C314N4B7 Datasheet PDF : 153 Pages
| |||
ST72334J/N, ST72314J/N, ST72124J
MISCELLANEOUS REGISTERS (Cont’d)
MISCELLANEOUS REGISTER 2 (MISCR2)
Read /Write
Reset Value: 0000 0000 (00h)
7
0
-
- BC1 BC0 -
- SSM SSI
Bit 7:6 = Reserved Must always be cleared
Bit 5:4 = BC[1:0] Beep control
These 2 bits select the PF1 pin beep capability.
Beep mode with fOSC=16MHz
Off
BC1 BC0
00
~2-KHz
~1-KHz
~500-Hz
Output
Beep signal
~50% duty cycle
01
10
11
The beep output signal is available in ACTIVE-
HALT mode but has to be disabled to reduce the
consumption.
Bit 3:2 = Reserved Must always be cleared
Bit 1 = SSM SS mode selection
It is set and cleared by software.
0: Normal mode - SS uses information coming
from the SS pin of the SPI.
1: I/O mode, the SPI uses the information stored
into bit SSI.
Bit 0 = SSI SS internal mode
This bit replaces pin SS of the SPI when bit SSM is
set to 1. (see SPI description). It is set and cleared
by software.
Table 10. Miscellaneous Register Map and Reset Values
Address
(Hex.)
Register
Label
0020h
0040h
MISCR1
Reset Value
MISCR2
Reset Value
7
IS11
0
0
6
IS10
0
0
5
MCO
0
BC1
0
4
IS21
0
BC0
0
3
IS20
0
0
2
CP1
0
0
1
CP0
0
SSM
0
0
SMS
0
SSI
0
48/153
Share Link: 