ST72334J/N, ST72314J/N, ST72124J
SERIAL COMMUNICATIONS INTERFACE (Cont’d)
Figure 48. SCI Block Diagram
TDO
RDI
Write
Transmit Data Register (TDR)
Read
(DATA REGISTER) DR
Received Data Register (RDR)
Transmit Shift Register
Received Shift Register
CR1
R8 T8 - M WAKE - -
-
TRANSMIT
CONTROL
WAKE
UP
UNIT
CR2
TIE TCIE RIE ILIE TE RE RWU SBK
RECEIVER
CONTROL
RECEIVER
CLOCK
SR
TDRE TC RDRF IDLE OR NF FE -
SCI
INTERRUPT
CONTROL
TRANSMITTER
CLOCK
fCPU
/16
/2
/PR
TRANSMITTER RATE
CONTROL
BRR
SCP1SCP0 SCT2 SCT1 SCT0 SCR2 SCR1SCR0
RECEIVER RATE
CONTROL
CONVENTIONAL BAUD RATE GENERATOR
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