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ST10F276 View Datasheet(PDF) - STMicroelectronics

Part Name
Description
Manufacturer
ST10F276 Datasheet PDF : 229 Pages
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Internal Flash memory
4
Internal Flash memory
ST10F276
4.1
Overview
The on-chip Flash is composed by two matrix modules each one containing one array
divided in two banks that can be read and modified independently one of the other: one
bank can be read while another bank is under modification.
Figure 4. Flash modules structure
IFLASH (Module I)
Control section
XFLASH (Module X)
Bank 1: 128 Kbyte
program memory
HV and Ref.
generator
Bank 3: 128 Kbyte
program memory
Bank 0: 384 Kbyte
program memory
+
8 Kbyte test-Flash
Program/erase
controller
Bank 2: 192 Kbyte
program memory
4.2
4.2.1
I-BUS interface
X-BUS interface
The write operations of the 4 banks are managed by an embedded Flash program/erase
controller (FPEC). The high voltages needed for program/erase operations are internally
generated.
The data bus is 32-bit wide. Due to ST10 core architecture limitation, only the first
512 Kbytes are accessed at 32-bit (internal Flash bus, see I-BUS), while the remaining
320 Kbytes are accessed at 16-bit (see X-BUS).
Functional description
Structure
The following table shows the address space reserved to the Flash module.
Table 2. Flash modules absolute mapping
Description
Addresses
IFLASH sectors
0x00 0000 to 0x08 FFFF
XFLASH sectors
0x09 0000 to 0x0D FFFF
Registers and Flash internal reserved
area
0x0E 0000 to 0x0E FFFF
Size
512 Kbyte
320 Kbyte
64 Kbyte
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