DatasheetQ Logo
Electronic component search and free download site. Transistors,MosFET ,Diode,Integrated circuits

PIC16C717-I/SS View Datasheet(PDF) - Microchip Technology

Part Name
Description
Manufacturer
PIC16C717-I/SS Datasheet PDF : 200 Pages
First Prev 101 102 103 104 105 106 107 108 109 110 Next Last
PIC16C717/770/771
9.2.15 CLOCK ARBITRATION
Clock arbitration occurs when the master, during any
receive, transmit or repeated start/stop condition, de-
asserts the SCL pin (SCL allowed to float high). When
the SCL pin is allowed to float high, the baud rate gen-
erator (BRG) is suspended from counting until the SCL
pin is actually sampled high. When the SCL pin is sam-
pled high, the baud rate generator is reloaded with the
contents of SSPADD<6:0> and begins counting. This
ensures that the SCL high time will always be at least
one BRG rollover count in the event that the clock is
held low by an external device (Figure 9-30).
9.2.16 SLEEP OPERATION
While in sleep mode, the I2C module can receive
addresses or data, and when an address match or
complete byte transfer occurs, wake the processor from
sleep ( if the SSP interrupt is enabled).
9.2.17 EFFECTS OF A RESET
A reset disables the MSSP module and terminates the
current transfer.
FIGURE 9-30: CLOCK ARBITRATION TIMING IN MASTER TRANSMIT MODE
BRG overflow,
Release SCL,
If SCL = 1 Load BRG with
SSPADD<6:0>, and start count
to measure high time interval
BRG overflow occurs,
Release SCL, Slave device holds SCL low.
SCL = 1 BRG starts counting
clock high interval.
SCL
SCL line sampled once every machine cycle (TOSC 4).
Hold off BRG until SCL is sampled high.
SDA
TBRG
TBRG
TBRG
DS41120A-page 102
Advanced Information
© 1999 Microchip Technology Inc.

Share Link: 

datasheetq.com  [ Privacy Policy ]Request Datasheet ] [ Contact Us ]