PIC16C717/770/771
FIGURE 9-33: BUS COLLISION DURING START CONDITION (SCL = 0)
SDA
SDA = 0, SCL = 1
TBRG
TBRG
SCL
Set SEN, enable start
sequence if SDA = 1, SCL = 1
SEN
BCLIF
SCL = 0 before BRG time out,
Bus collision occurs, Set BCLIF.
S
’0’
SSPIF ’0’
SCL = 0 before SDA = 0,
Bus collision occurs, Set BCLIF.
Interrupts cleared
in software.
’0’
’0’
FIGURE 9-34: BRG RESET DUE TO SDA COLLISION DURING START CONDITION
SDA
SDA = 0, SCL = 1
Set S
Less than TBRG
TBRG
SDA pulled low by other master.
Reset BRG and assert SDA
Set SSPIF
SCL
SEN
BCLIF ’0’
s
SCL pulled low after BRG
Timeout
Set SEN, enable start
sequence if SDA = 1, SCL = 1
S
SSPIF
SDA = 0, SCL = 1
Set SSPIF
Interrupts cleared
in software.
© 1999 Microchip Technology Inc.
Advanced Information
DS41120A-page 105