PIC16LC717T-I/SO View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC16LC717T-I/SO

18/20-Pin, 8-Bit CMOS Microcontrollers with 10/12-Bit A/D

Microchip Technology 

PIC16C717/770/771

2.2.2 SPECIAL FUNCTION REGISTERS

The Special Function Registers are registers used by

the CPU and Peripheral Modules for controlling the

desired operation of the device. These registers are

implemented as static RAM. A list of these registers is

given in Table 2-1.

The special function registers can be classified into two

sets; core (CPU) and peripheral. Those registers asso-

ciated with the core functions are described in detail in

this section. Those related to the operation of the

peripheral features are described in detail in that

peripheral feature section.

TABLE 2-1:

Address Name

PIC16C717/770/771 SPECIAL FUNCTION REGISTER SUMMARY

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on: Value on all

POR, other resets

BOR

(2)

Bank 0

00h(3)

INDF

Addressing this location uses contents of FSR to address data memory (not a physical register)

0000 0000 0000 0000

01h

TMR0

Timer0 module’s register

xxxx xxxx uuuu uuuu

02h(3)

PCL

Program Counter's (PC) Least Significant Byte

0000 0000 0000 0000

03h(3) STATUS

IRP

RP1

RP0

TO

PD

Z

DC

C

0001 1xxx 000q quuu

04h(3)

FSR

Indirect data memory address pointer

xxxx xxxx uuuu uuuu

05h

PORTA

RA7

RA6

RA5

RA4

RA3

RA2

RA1

RA0 xxxx 0000 uuuu 0000

06h

PORTB

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0 xxxx xx00 uuuu uu00

07h

—

Unimplemented

—

—

08h

—

Unimplemented

—

—

09h

0Ah(1,3)

0Bh(3)

—

PCLATH

INTCON

Unimplemented

—

—

GIE

PEIE

—

T0IE

Write Buffer for the upper 5 bits of the Program Counter

INTE

RBIE

T0IF

INTF

RBIF

—

—

---0 0000 ---0 0000

0000 000x 0000 000u

0Ch

PIR1

—

ADIF

—

—

SSPIF CCP1IF TMR2IF TMR1IF -0-- 0000 -0-- 0000

0Dh

PIR2

LVDIF

—

—

—

BCLIF

—

—

—

0--- 0--- 0--- 0---

0Eh

TMR1L

Holding register for the Least Significant Byte of the 16-bit TMR1 register

xxxx xxxx uuuu uuuu

0Fh

TMR1H

Holding register for the Most Significant Byte of the 16-bit TMR1 register

xxxx xxxx uuuu uuuu

10h

T1CON

—

—

T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu

11h

TMR2

Timer2 module’s register

0000 0000 0000 0000

12h

T2CON

—

TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000

13h

SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register

xxxx xxxx uuuu uuuu

14h

SSPCON

WCOL SSPOV SSPEN

CKP

SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000

15h

CCPR1L Capture/Compare/PWM Register1 (LSB)

xxxx xxxx uuuu uuuu

16h

CCPR1H Capture/Compare/PWM Register1 (MSB)

xxxx xxxx uuuu uuuu

17h

CCP1CON PWM1M1 PWM1M0 DC1B1

DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 0000 0000

18h

—

Unimplemented

—

—

19h

—

Unimplemented

—

—

1Ah

—

Unimplemented

—

—

1Bh

—

Unimplemented

—

—

1Ch

—

Unimplemented

—

—

1Dh

—

Unimplemented

—

—

1Eh

ADRESH A/D High Byte Result Register

xxxx xxxx uuuu uuuu

1Fh

ADCON0

ADCS1 ADCS0

CHS2

CHS1

CHS0 GO/DONE CHS3

ADON 0000 0000 0000 0000

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as ’0’.

Shaded locations are unimplemented, read as ‘0’.

Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose con-

tents are transferred to the upper byte of the program counter.

2: Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset.

3: These registers can be addressed from any bank.

© 1999 Microchip Technology Inc.

Advanced Information

DS41120A-page 13

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