PIC16LC717T-I/SO View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC16LC717T-I/SO

18/20-Pin, 8-Bit CMOS Microcontrollers with 10/12-Bit A/D

Microchip Technology 

PIC16C717/770/771

TABLE 2-1: PIC16C717/770/771 SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Address Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on: Value on all

POR, other resets

BOR

(2)

Bank 1

80h(3)

INDF

Addressing this location uses contents of FSR to address data memory (not a physical register)

0000 0000 0000 0000

81h

OPTION_REG RBPU INTEDG T0CS

T0SE

PSA

PS2

PS1

PS0 1111 1111 1111 1111

82h(3)

PCL

Program Counter’s (PC) Least Significant Byte

0000 0000 0000 0000

83h(3) STATUS

IRP

RP1

RP0

TO

PD

Z

DC

C

0001 1xxx 000q quuu

84h(3)

FSR

Indirect data memory address pointer

xxxx xxxx uuuu uuuu

85h

TRISA

PORTA Data Direction Register

1111 1111 1111 1111

86h

TRISB

PORTB Data Direction Register

1111 1111 1111 1111

87h

—

Unimplemented

—

—

88h

—

Unimplemented

—

—

89h

8Ah(1,3)

8Bh(3)

—

PCLATH

INTCON

Unimplemented

—

—

GIE

PEIE

—

T0IE

Write Buffer for the upper 5 bits of the Program Counter

INTE

RBIE

T0IF

INTF

RBIF

—

—

---0 0000 ---0 0000

0000 000x 0000 000u

8Ch

PIE1

—

ADIE

—

—

SSPIE CCP1IE TMR2IE TMR1IE -0-- 0000 -0-- 0000

8Dh

PIE2

LVDIE

—

—

—

BCLIE

—

—

—

0--- 0--- 0--- 0---

8Eh

PCON

—

—

—

—

OSCF

—

POR

BOR ---- 1-qq ---- 1-uu

8Fh

—

Unimplemented

—

—

90h

—

Unimplemented

—

—

91h

SSPCON2

GCEN ACKSTAT ACKDT

ACKEN

RCEN

PEN

RSEN

SEN 0000 0000 0000 0000

92h

PR2

Timer2 Period Register

93h

SSPADD Synchronous Serial Port (I2C mode) Address Register

1111 1111 1111 1111

0000 0000 0000 0000

94h

SSPSTAT

SMP

CKE

D/A

P

S

R/W

UA

BF

0000 0000 0000 0000

95h

WPUB

PORTB Weak Pull-up Control

1111 1111 1111 1111

96h

IOCB

PORTB Interrupt on Change Control

1111 0000 1111 0000

97h

P1DEL

PWM 1 Delay value

0000 0000 0000 0000

98h

—

Unimplemented

—

—

99h

—

Unimplemented

—

—

9Ah

—

Unimplemented

—

—

9Bh

REFCON

VRHEN VRLEN VRHOEN VRLOEN

—

—

—

—

0000 ---- 0000 ----

9Ch

LVDCON

—

9Dh

ANSEL

—

BGST

LVDEN

Analog Channel Select

LVV3

LVV2

LVV1

LVV0

--00 0101 --00 0101

1111 1111 1111 1111

9Eh

ADRESL A/D Low Byte Result Register

xxxx xxxx uuuu uuuu

9Fh

ADCON1

ADFM VCFG2 VCFG1

VCFG0

0000 0000 0000 0000

Legend:

Note 1:

2:

3:

x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as ’0’.

Shaded locations are unimplemented, read as ‘0’.

The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose con-

tents are transferred to the upper byte of the program counter.

Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset.

These registers can be addressed from any bank.

DS41120A-page 14

Advanced Information

© 1999 Microchip Technology Inc.

Share Link: