PIC16LC717T-I/SO View Datasheet(PDF) - Microchip Technology
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PIC16LC717T-I/SO Datasheet PDF : 200 Pages
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8.2.4 SPECIAL EVENT TRIGGER
In this mode, an internal hardware trigger is generated,
which may be used to initiate an action.
The special event trigger output of ECCP resets the
TMR1 register pair. This allows the CCPR1 register to
effectively be a 16-bit programmable period register for
Timer1.
The special event trigger output of ECCP module will
also start an A/D conversion if the A/D module is
enabled.
Note: The special event trigger will not set the
interrupt flag bit TMR1IF (PIR1<0>).
PIC16C717/770/771
FIGURE 8-2:
COMPARE MODE
OPERATION BLOCK
DIAGRAM
Special event trigger will:
reset Timer1, but not set interrupt flag bit TMR1IF (PIR1<0>).
Special Event Trigger
Set flag bit CCP1IF
(PIR1<2>)
CCPR1H CCPR1L
Q
RB3/CCP1/
P1A Pin
TRISB<3>
Output Enable
S Output
R Logic match
CCP1CON<3:0>
Mode Select
Comparator
TMR1H TMR1L
TABLE 8-2: REGISTERS ASSOCIATED WITH CAPTURE, COMPARE AND TIMER1
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR,
BOR
INTCON
PIR1
PIE1
GIE
PSPIF(1)
PSPIE(1)
PEIE
ADIF
ADIE
T0IE
RCIF
RCIE
INTE
TXIF
TXIE
RBIE
SSPIF
SSPIE
T0IF
CCP1IF
CCP1IE
INTF
TMR2IF
TMR2IE
RBIF
TMR1IF
TMR1IE
0000 000x
0000 0000
0000 0000
TRISB
PORTB Data Direction Register
1111 1111
TMR1L
Holding register for the Least Significant Byte of the 16-bit TMR1 register
xxxx xxxx
TMR1H
Holding register for the Most Significant Byte of the 16-bit TMR1register
xxxx xxxx
T1CON
—
—
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000
CCPR1L Capture/Compare/PWM register1 (LSB)
xxxx xxxx
CCPR1H Capture/Compare/PWM register1 (MSB)
xxxx xxxx
CCP1CON PWM1M1 PWM1M0 DC1B1
DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000
Legend: x = unknown, u = unchanged, - = unimplemented read as ’0’. Shaded cells are not used by Capture and Timer1.
Value on
all other
resets
0000 000u
0000 0000
0000 0000
1111 1111
uuuu uuuu
uuuu uuuu
--uu uuuu
uuuu uuuu
uuuu uuuu
0000 0000
© 1999 Microchip Technology Inc.
Advanced Information
DS41120A-page 57
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