PIC16C717/770/771
8.3.4 OUTPUT POLARITY CONFIGURATION
The CCP1M<1:0> bits in the CCP1CON register allow
user to choose the logic conventions (asserted high/
low) for each of the outputs. See Register 8-1 for fur-
ther details.
FIGURE 8-6: HALF-BRIDGE PWM OUTPUT
Period
Period
P1A(2)
Duty Cycle
td
td
P1B(2)
(1)
(1)
(1)
td = Deadband Delay
Note 1: At this time, the TMR2 register is equal to the PR2 register.
2: Output signals are shown as asserted high.
The PWM output polarities must be selected before the
PWM outputs are enabled. Charging the polarity con-
figuration while the PWM outputs are active is not rec-
ommended, since it may result in unpredictable
operation.
DS41120A-page 60
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© 1999 Microchip Technology Inc.