PIC16LC717T-I/SO View Datasheet(PDF) - Microchip Technology
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PIC16LC717T-I/SO Datasheet PDF : 200 Pages
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PIC16C717/770/771
8.3.7 SYSTEM IMPLEMENTATION
8.3.9 SET UP FOR PWM OPERATION
When the ECCP module is used in the PWM mode, the
application hardware must use the proper external pull-
up and/or pull-down resistors on the PWM output pins.
When the microcontroller powers up, all of the I/O pins
are in the high-impedance state. The external pull-up
and pull-down resistors must keep the power switch
devices in the off state until the microcontroller drives
the I/O pins with the proper signal levels, or activates
the PWM output(s).
8.3.8 START-UP CONSIDERATIONS
Prior to enabling the PWM outputs, the P1A, P1B, P1C
and P1D latches may not be in the proper states.
Enabling the TRISB bits for output at the same time
with the CCP module may cause damage to the power
switch devices. The CCP1 module must be enabled in
the proper output mode with the TRISB bits enabled as
inputs. Once the CCP1 completes a full PWM cycle, the
P1A, P1B, P1C and P1D output latches are properly
initialized. At this time, the TRISB bits can be enabled
for outputs to start driving the power switch devices.
The completion of a full PWM cycle is indicated by the
TMR2IF bit going from a ’0’ to a ’1’.
The following steps should be taken when configuring
the ECCP module for PWM operation:
1. Configure the PWM module:
a) Disable the CCP1/P1A, P1B, P1C and/or
P1D outputs by setting the respective
TRISB bits.
b) Set the PWM period by loading the PR2
register.
c) Set the PWM duty cycle by loading the
CCPR1L register and CCP1CON<5:4>
bits.
d) Configure the ECCP module for the desired
PWM operation by loading the CCP1CON
register. With the CCP1M<3:0> bits select
the active high/low levels for each PWM
output. With the PWM1M<1:0> bits select
one of the available output modes: Single,
Half-Bridge, Full-Bridge, Forward or Full-
Bridge Reverse.
e) For Half-Bridge output mode, set the dead-
band delay by loading the P1DEL register.
2. Configure and start TMR2:
a) Clear the TMR2 interrupt flag bit by clearing
the TMR2IF bit in the PIR1 register.
b) Set the TMR2 prescale value by loading the
T2CKPS<1:0> bits in the T2CON register.
c) Enable Timer2 by setting the TMR2ON bit
in the T2CON register.
3. Enable PWM outputs after a new cycle has
started:
a) Wait until TMR2 overflows (TMR2IF bit
becomes a ’1’). The new PWM cycle begins
here.
b) Enable the CCP1/P1A, P1B, P1C and/or
P1D pin outputs by clearing the respective
TRISB bits.
TABLE 8-3: REGISTERS ASSOCIATED WITH PWM
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR,
BOR
Value on
all other
resets
0Bh, 8Bh,
10Bh,
18Bh
0Ch
8Ch
86h, 186h
11h
92h
12h
15h
17h
97h
Legend:
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x 0000 000u
PIR1
—
ADIF
—
—
SSPIF
CCP1IF
TMR2IF
TMR1IF -0-- 0000 -0-- 0000
PIE1
—
ADIE
—
—
SSPIE
CCP1IE TMR2IE TMR1IE -0-- 0000 -0-- 0000
TRISB
PORTB Data Direction Register
1111 1111 1111 1111
TMR2
Timer2 register
0000 0000 0000 0000
PR2
Timer2 period register
1111 1111 1111 1111
T2CON
—
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
CCPR1L Capture/Compare/PWM register1 (LSB)
xxxx xxxx uuuu uuuu
CCP1CON PWM1M1 PWM1M0 DC1B1
DC1B0
CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 0000 0000
P1DEL
PWM1 Delay value
0000 0000 0000 0000
Legend: x = unknown, u = unchanged, - = unimplemented read as ’0’. Shaded cells are not used by Capture and Timer1.
DS41120A-page 66
Advanced Information
© 1999 Microchip Technology Inc.
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