PIC16LC717T-I/SO View Datasheet(PDF) - Microchip Technology
Part Name
Description
Manufacturer
PIC16LC717T-I/SO Datasheet PDF : 200 Pages
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PIC16C717/770/771
REGISTER 9-3: SYNC SERIAL PORT CONTROL REGISTER2 (SSPCON2: 91h)
R/W-0
R/W-0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
GCEN
bit7
bit 7:
ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN
R = Readable bit
bit0 W = Writable bit
U = Unimplemented bit, Read
as ‘0’
- n = Value at POR reset
GCEN: General Call Enable bit (In I2C slave mode only)
1 = Enable interrupt when a general call address (0000h) is received in the SSPSR.
0 = General call address disabled.
bit 6: ACKSTAT: Acknowledge Status bit (In I2C master mode only)
In master transmit mode:
1 = Acknowledge was not received from slave
0 = Acknowledge was received from slave
bit 5: ACKDT: Acknowledge Data bit (In I2C master mode only)
In master receive mode:
Value that will be transmitted when the user initiates an Acknowledge sequence at the end of a receive.
1 = Not Acknowledge
0 = Acknowledge
bit 4: ACKEN: Acknowledge Sequence Enable bit (In I2C master mode only).
In master receive mode:
1 = Initiate Acknowledge sequence on SDA and SCL pins, and transmit ACKDT data bit. Automatically
cleared by hardware.
0 = Acknowledge sequence idle
bit 3:
RCEN: Receive Enable bit (In I2C master mode only).
1 = Enables Receive mode for I2C
0 = Receive idle
bit 2: PEN: Stop Condition Enable bit (In I2C master mode only).
SCK release control
1 = Initiate Stop condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Stop condition idle
bit 1: RSEN: Repeated Start Condition Enabled bit (In I2C master mode only)
1 = Initiate Repeated Start condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Repeated Start condition idle.
bit 0:
SEN: Start Condition Enabled bit (In I2C master mode only)
1 = Initiate Start condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Start condition idle.
Note:
For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I2C module is not in the idle mode, this bit may not be set (no
spooling) and the SSPBUF may not be written (or writes to the SSPBUF are disabled).
DS41120A-page 70
Advanced Information
© 1999 Microchip Technology Inc.
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