ST10R272L - SERIAL CHANNELS
various commonly used baud rates together with the required reload values and the deviation
errors compared to the intended baudrate.
S0BRS = ‘0’, fCPU = 50MHz
S0BRS = ‘1’, fCPU = 50MHz
Baud Rate
(Baud)
Deviation Error
Reload Value
Baud Rate
(Baud)
Deviation Error
Reload Value
1562500
56000
38400
19200
9600
4800
2400
1200
600
190
0.0%
+3.3%
+1.7%
+0.5%
+0.5%
+0.2%
0.0%
0.0%
0.0%
+0.4%
/ 0.0% 0000H / 0000H 1041666
/ -0.4% 001AH / 001BH 56000
/ -0.8% 0027H / 0028H 38400
/ -0.8% 0050H / 0051H 19200
/ -0.1% 00A1H/ 00A2H 9600
/ -0.1% 0144H / 0145H 4800
/ -0.1% 028AH / 028BH 2400
/ -0.1% 0515H / 0516H 1200
/ 0.0% 0A2BH / 0A2CH 600
/+0.4% 1FFFH / 1FFFH 75
127
0.0%
+3.3%
+0.5%
+0.5%
+0.5%
0.0%
0.0%
0.0%
0.0%
0.0%
+0.1%
/ 0.0% 0000H / 0000H
/ -2.1% 0011H / 0012H
/ -3.1% 001AH / 001BH
/-1.4% 0035H / 0036H
/ -0.5% 006BH / 006CH
/ -0.5% 00D8H / 00D9H
/ -0.2% 01B1H / 01B2H
/ -0.1% 0363H / 0364H
/ -0.1% 06C7H / 06C8H
/ 0.0% 363FH / 3640H
/ +0.1% 1FFFH / 1FFFH
Table 10 Commonly used baud rates, required reload values and deviation errors
SSP transmits 1...3 bytes or receives 1 byte after sending 1...3 bytes synchronously to a shift
clock which is generated by the SSP. The SSP can start shifting with the LSB or with the MSB
and is used to select shifting and latching clock edges, and clock polarity. Up to two chip select
lines may be activated in order to direct data transfers to one or both of two peripheral devices.
When the SSP is enabled, the four upper pins of Port4 can not be used as general purpose
IO. Note that the segment address selection done via the system start-up configuration during
reset has priority and overrides the SSP functions on these pins.
SSPCKS Value
Synchronous baud rate
000
SSP clock = CPU clock divided by 2
25 MBit/s
001
SSP clock = CPU clock divided by 4
12.5 MBit/s
010
SSP clock = CPU clock divided by 8
6.25 MBit/s
Table 11 Synchronous baud rate and SSPCKS reload values
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