ST10R272L - ELECTRICAL CHARACTERISTICS
Remarks on 5 volt tolerant (5T) and 5 volt fail-safe (5S) pins
The 5V tolerant input and output pins can sustain an absolute maximum external voltage of
5.5V.
However, signals on unterminated bus lines might have overshoot above 5.5V, presenting
latchup and hot carrier risks. While these risks are under evaluation, observe the following se-
curity recommendations:
• Maximum peak voltage on 5V tolerant pin with respect to ground (VSS)= +6 V
• If the ringing of the external signal exceeds 6V, then clip the signal to the 5V supply.
Power supply failure condition
The power supply failure condition is a state where the chip is NOT supplied but is connected
to active signal lines. There are several cases:
• 3.3V external lines on 3.3V (3T) pin on the non powered chip: ...............NOT Acceptable
• 3.3V external lines on 5V tolerant (5T) pin on the non powered chip: ............. Acceptable
The 5V tolerant buffer do not leak: external signals not altered. No reliability problem.
• 3.3V external lines on 5V fail-safe (5S) pin on the non powered chip: ............ Acceptable
The 5V tolerant buffer do not leak: external signals not altered. No reliability problem.
• 5.5V external lines on 5V tolerant (5T) pin on the non powered chip: ............. Acceptable
For VERY SHORT times only: the buffers do not leak (external signals not altered) but
there is a fast degradation of the gate oxides in the buffers. The total maximum time under
this stress condition is 2 days. This limits this configuration to short power-up/down
sequences. For 10 year life time, the maximum duty factor is 1/1800 allowing e.g. a
maximum stress duration of 48 seconds per day.
• 5.5V external lines on 5V fail-safe (5S) pin on the non powered chip: ............ Acceptable
• 6V transient signals on 5V tolerant (5T) pin on the non powered chip: ...NOT Acceptable
• 6V transient signals on 5V fail-safe (5S) pin on the non powered chip:.......... Acceptable
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