ST10R272 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST10R272

16-BIT LOW VOLTAGE ROMLESS MCU WITH MAC

STMicroelectronics 

ST10R272L - ELECTRICAL CHARACTERISTICS

P0.15-13 (P0H.7-5)

CPU frequency

fCPU = fXTAL * F

External clock

input range 10-

50MHz

Notes

1

0

0

FXTAL * 5

0

1

1

FXTAL * 1

2 to 10 MHz

1 to 50 MHz

Direct drive 1)

0

1

0

0

0

1

0

0

0

FXTAL * 1.5

FXTAL / 2

FXTAL * 2.5

6.66 to 33.33 MHz

2 to 100 MHz

4 to 20 MHz

CPU clock via 2:1 prescaler

Table 15 CPU clock generation mechanisms

1) The maximum depends on the duty cycle of the external clock signal. The maxi-

mum input frequency is 25 MHz when using an external crystal oscillator, but

higher frequencies can be applied with an external clock source.

Prescaler operation

Set when pins P0.15-13 (P0H.7-5) equal ’001’ during reset, the CPU clock is derived from the

internal oscillator (input clock signal) by a 2:1 prescaler.

The frequency of fCPU is half the frequency of fXTAL and the high and low time of fCPU (i.e. the

duration of an individual TCL) is defined by the period of the input clock fXTAL.

The timings listed in the AC characteristics that refer to TCLs therefore can be calculated

using the period of fXTAL for any TCL.

Note that if the bit OWDDIS in SYSCON register is cleared, the PLL runs on its free-running

frequency and delivers the clock signal for the Oscillator Watchdog. If bit OWDDIS is set, then

the PLL is switched off.

Direct drive

When pins P0.15-13 (P0H.7-5) equal ’011’ during reset, the on-chip phase locked loop is

disabled and the CPU clock is driven from the internal oscillator with the input clock signal.

The frequency of fCPU directly follows the frequency of fXTAL so the high and low time of fCPU

(i.e. the duration of an individual TCL) is defined by the duty cycle of the input clock fXTAL.

The TCL timing below must be calculated using the minimum possible TCL which can be

calculated by the formula: TCLmin= 1 ⁄ fXTAL × DCmin(DC = duty cycle )

For two consecutive TCLs the deviation caused by the duty cycle of fXTAL is compensated so

the duration of 2TCL is always 1/fXTAL. Therefore, the minimum value TCLmin has to be used

only once for timings that require an odd number of TCLs (1,3,...). Timings that require an

even number of TCLs (2,4,...) may use the formula: 2TCL = 1 ⁄ fXTAL .

48/77

1

Share Link: