ST5090TQFPTR View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
ST5090TQFPTR Datasheet PDF : 29 Pages
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ABSOLUTE MAXIMUM RATINGS
Parameter
VCC to GND
Voltage at MIC (VCC ≤ 5.5V)
Current at VFr and VLr
Current at any digital output
Voltage at any digital input (VCC ≤ 5.5V); limited at + 50mA
Storage temperature range
Lead Temperature (wave soldering, 10s)
ST5090
Value
7
VCC +1 to GND -1
+ 100
+ 50
VCC + 1 to GND - 1
- 65 to + 150
+ 260
Unit
V
V
mA
mA
V
°C
°C
TIMING SPECIFICATIONS (unless otherwise specified, VCC = 3.3V + 10%or 5V ± 10%, TA = –30°C to 85°C ;
typical characteristics are specified VCC = 3.3V, TA = 25 °C;
all signals are referenced to GND, see Note 5 for timing definitions)
NOTICE: All timing specifications can be changed.
MASTER CLOCK TIMING
Symbol
fMCLK
Parameter
Frequency of MCLK
tWMH
tWML
tRM
tFM
Period of MCLK high
Period of MCLK low
Rise Time of MCLK
Fall Time of MCLK
Test Condition
Selection of frequency is
programmable (see table 2)
Measured from VIH to VIH
Measured from VIL to VIL
Measured from VIL to VIH
Measured from VIH to VIL
Min .
80
80
Typ.
512
1.536
2.048
2.560
Max.
30
30
Unit
kHz
MHz
MHz
MHz
ns
ns
ns
ns
PCM INTERFACE TIMING
Symbol
Parameter
Test Condition
Min. Typ. Max. Unit
tHMF
Hold Time MCLK low to FS low
tSFM
Setup Time, FS high to MCLK
low
0
ns
30
ns
tDMD
Delay Time, MCLK high to data Load = 100 pf
valid
100
ns
tDMZ
Delay Time, MCLK low to DX
disabled
10
100
ns
tDFD
Delay Time, FS high to data valid Load = 100 pf ;
Applies only if FS rises later
than MCLK rising edge in Non
Delayed Mode only
100
ns
tSDM
Setup Time, DR valid to MCLK
receive edge
20
ns
tHMD
Hold Time, MCLK low to DR
invalid
10
ns
tHMFR
tSFMR
Hold Time MCLK High to FS low
Setup Time, FS high to MCLK High
30
ns
30
ns
tDMDR
Delay Time, MCLK low to data valid Load = 100pF
100
ns
tDMZR
Delay Time, MCLK High to DX
disabled
10
100
ns
tHMDR
Hold Time, MCLK High to DR
invalid
20
ns
19/29
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