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ST62T28CM6 View Datasheet(PDF) - STMicroelectronics

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Description
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ST62T28CM6 Datasheet PDF : 84 Pages
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ST62T28C/E28C
INTERRUPTS (Cont’d)
Interrupt Polarity Register (IPR)
Address: DAh — Read/Write
7
generates interrupt on rising edge. At reset, IPR is
cleared and all port interrupts are not inverted (e.g.
Port C generates interrupts on falling edges).
0
Bit 7 - Bit 4 = Unused.
-
-
-
- PortD PortC PortA PortB Bit 3 = Port D Interrupt Polarity.
In conjunction with I/O register ESB bit, the polarity
of I/O pins triggered interrupts can be selected by
setting accordingly the Interrupt Polarity Register
(IPR). If a bit in IPR is set to one the corresponding
port interrupt is inverted (e.g. IPR bit 2 = A; port C
Bit 2 = Port C Interrupt Polarity.
Bit 1= Port A Interrupt Polarity.
Bit 0 = Port B Interrupt Polarity.
Tables 11. I/O Interrupts selections according to IPR, IOR programming
GEN
1
1
1
1
1
1
1
1
0
IPR3
0
0
0
0
1
1
1
1
X
IPR0
0
0
1
1
0
0
1
1
X
IOR5
0
1
0
1
0
1
0
1
X
Port B occurrence
falling edge
rising edge
rising edge
falling edge
falling edge
rising edge
rising edge
falling edge
Disabled
Port D occurrence
falling edge
rising edge
falling edge
rising edge
rising edge
falling edge
rising edge
falling edge
Disabled
Interrupt
source
2
GEN
1
1
1
1
0
IPR1
0
0
1
1
X
IOR6
0
1
0
1
X
Port A occurrence
falling edge
low level
rising edge
high level
Disabled
Interrupt
source
1
IPR2
0
1
Port C occurrence
falling edge
rising edge
Interrupt source
0
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