ST62P32BQ3 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST62P32BQ3

8-BIT OTP/EPROM MCUs WITH A/D CONVERTER, 16-BIT AUTO-RELOAD TIMER, EEPROM, SPI AND UART

STMicroelectronics 

ST62T32B ST62E32B

TIMINGS MEASUREMENT MODES(Cont’d)

CP2 triggered restart mode with CP2 event de-

tection.

This mode is enabled for RLDSEL2=1 and

RLDSEL1=0.

As long as RUNRES bit is set, an external event

on CP2 pin generates both, at first the capture into

CP, and then the reload from RLCP. Capture into

CP on CP2 event is enabled only if CP2FLG and

CP2ERR are cleared, otherwise only reload func-

tions from RLCP are performed.

An external event on CP1 activates CP1FLG or

CP1ERR flags without any impact on the reload or

capture functions.

Note: After Reset, the first CP2 event will capture

the 0000h state of the counter into CP and then

will restart the counter after loading it from RLCP.

CP2FLG flag must always be cleared to execute

another capture into CP.

Software triggered restart mode with CP2

event detection.

This mode is enabled for RLDSEL2=0 and

RLDSEL1=0.

RUNRES bit setting initiates the reload and startup

of the downcounting, while CP2 is used as strobe

source for the CT capture into CP register.

Figure 31. CP2 Triggered Restart Mode with CP2 Event Detection

CP1

Set CP1FLG

CP2

First Capture CT into CP

Then Reload CT from RLCP

Set CP2FLG

Set CP1ERR

No action

Reload CT from RLCP

Set CP2ERR

Reload CT from RLCP

V R020 07C

Figure 32. Software Triggered Restart Mode with CP2 Event Detection

COUNTER

CT

0000h

0000h

RUNRES

Load Counter from RLCP and Startup

CP1

CP1 disabled

Set CP1FLG

Software Reset

Set CP1ERR

CP1 disabled

CP2

CP2 disabled

Capture CT into CP

Set CP2FLG

Set CP2ERR

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