ST72262G1 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST72262G1

8-BIT MCU WITH FLASH OR ROM MEMORY, ADC, TWO 16-BIT TIMERS, I2C, SPI, SCI INTERFACES

STMicroelectronics 

ST72260G, ST72262G, ST72264G

SYSTEM INTEGRITY MANAGEMENT (Cont’d)

6.4.5 Register Description

SYSTEM INTEGRITY (SI) CONTROL/STATUS REGISTER (SICSR)

Read /Write

Reset Value: 000x 000x (00h)

7

0

0

AVD AVD LVD

IE F RF

0

CSS CSS WDG

IE D RF

Bit 7 = Reserved, always read as 0.

Bit 6 = AVDIE Voltage Detector interrupt enable

This bit is set and cleared by software. It enables

an interrupt to be generated when the AVDF flag

changes (toggles). The pending interrupt informa-

tion is automatically cleared when software enters

the AVD interrupt routine.

0: AVD interrupt disabled

1: AVD interrupt enabled

Bit 5 = AVDF Voltage Detector flag

This read-only bit is set and cleared by hardware.

If the AVDIE bit is set, an interrupt request is gen-

erated when the AVDF bit changes value.

0: VDD over VIT+(AVD) threshold

1: VDD under VIT-(AVD) threshold

bit set). It is set and cleared by software.

0: Clock security system interrupt disabled

1: Clock security system interrupt enabled

When the CSS is disabled by OPTION BYTE, the

CSSIE bit has no effect.

Bit 1 = CSSD Clock security system detection

This bit indicates that the safe oscillator of the

Clock Security System block has been selected by

hardware due to a disturbance on the main clock

signal (fOSC). It is set by hardware and cleared by

reading the SICSR register when the original oscil-

lator recovers.

0: Safe oscillator is not active

1: Safe oscillator has been activated

When the CSS is disabled by OPTION BYTE, the

CSSD bit value is forced to 0.

Bit 0 = WDGRF Watchdog reset flag

This bit indicates that the last Reset was generat-

ed by the Watchdog peripheral. It is set by hard-

ware (watchdog reset) and cleared by software

(writing zero) or an LVD Reset (to ensure a stable

cleared state of the WDGRF flag when CPU

starts).

Combined with the LVDRF flag information, the

flag description is given by the following table.

Bit 4 = LVDRF LVD reset flag

This bit indicates that the last Reset was generat-

ed by the LVD block. It is set by hardware (LVD re-

set) and cleared by software (writing zero). See

WDGRF flag description for more details. When

the LVD is disabled by OPTION BYTE, the LVDRF

bit value is undefined.

RESET Sources

External RESET pin

Watchdog

LVD

Application Notes

LVDRF

0

0

1

WDGRF

0

1

X

Bit 3 = Reserved, must be kept cleared.

Bit 2 = CSSIE Clock security syst. interrupt enable

This bit enables the interrupt when a disturbance

is detected by the Clock Security System (CSSD

The LVDRF flag is not cleared when another RE-

SET type occurs (external or watchdog), the

LVDRF flag remains set to keep trace of the origi-

nal failure. In this case, a watchdog reset can be

detected by software while an external reset can

not.

Address

(Hex.)

Register

Label

7

6

5

4

3

2

1

0

0025h

SICSR

Reset Value

0

AVDIE

0

AVDF LVDRF

0

x

0

CSSIE

0

CSSD WDGRF

0

x

27/171

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