ST72P264G2M6/XXX View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST72P264G2M6/XXX

8-BIT MCU WITH FLASH OR ROM MEMORY, ADC, TWO 16-BIT TIMERS, I2C, SPI, SCI INTERFACES

STMicroelectronics 

ST72260G, ST72262G, ST72264G

11.4 SERIAL PERIPHERAL INTERFACE (SPI)

11.4.1 Introduction

The Serial Peripheral Interface (SPI) allows full-

duplex, synchronous, serial communication with

external devices. An SPI system may consist of a

master and one or more slaves or a system in

which devices may be either masters or slaves.

11.4.2 Main Features

s Full duplex synchronous transfers (on 3 lines)

s Simplex synchronous transfers (on 2 lines)

s Master or slave operation

s Six master mode frequencies (fCPU/4 max.)

s fCPU/2 max. slave mode frequency

s SS Management by software or hardware

s Programmable clock polarity and phase

s End of transfer interrupt flag

s Write collision, Master Mode Fault and Overrun

flags

11.4.3 General Description

Figure 47 shows the serial peripheral interface

(SPI) block diagram. There are 3 registers:

– SPI Control Register (SPICR)

– SPI Control/Status Register (SPICSR)

– SPI Data Register (SPIDR)

The SPI is connected to external devices through

3 pins:

– MISO: Master In / Slave Out data

– MOSI: Master Out / Slave In data

– SCK: Serial Clock out by SPI masters and in-

put by SPI slaves

– SS: Slave select:

This input signal acts as a ‘chip select’ to let

the SPI master communicate with slaves indi-

vidually and to avoid contention on the data

lines. Slave SS inputs can be driven by stand-

ard I/O ports on the master Device.

Figure 47. Serial Peripheral Interface Block Diagram

SPIDR

Data/Address Bus

Read

Read Buffer

Interrupt

request

MOSI

MISO

SOD

bit

SCK

8-Bit Shift Register

Write

7

SPIF WCOL OVR MODF 0

SPICSR 0

SOD SSM SSI

SPI

STATE

CONTROL

1

SS

0

MASTER

CONTROL

7

SPICR 0

SPIE SPE SPR2 MSTR CPOL CPHA SPR1 SPR0

SERIAL CLOCK

GENERATOR

SS

74/171

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