ST72F321M7 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
ST72F321M7
STMicroelectronics
ST72F321M7 Datasheet PDF : 185 Pages
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ST72321
15.4 FLASH REV “S” and ROM Rev “Y”
DEVICES ONLY
15.4.1 I/O Port D Configuration
When using an external quartz crystal or ceramic
resonator, the fOSC2 clock may be disturbed be-
cause the device goes into reserved mode control-
led by Port D.
This happens with either one of the following con-
figurations:
– PD[3:1]=010 while CSS and PLL options are
both disabled and PD4 is toggling
– PD[4:1]=1010 while CSS or PLL options are en-
abled
This is detailed in the following table:
CSS PLL PD[3:1]
OFF OFF 010
x ON
010
ON x
PD4
Tog-
gling
1
Clock
Disturbance
Max. 2 clock cy-
cles lost at each
rising or falling
edge of PD4
Max. 1 clock cy-
cle lost out of
every 16
15.5 ALL ROM DEVICES
15.5.1 LVD Operation
Depending on the operating conditions, especially
the VDD ramp up speed and ambient temperature,
in some cases the LVD may not start. When this
occurs, the MCU may operate outside the guaran-
teed functional area (see datasheet Figure 76)
without being forced into reset state.
In this case, proper use of the watchdog may
make it possible to recover through a watchdog re-
set and allow normal operations to resume.
Consequently, the LVD function is not guaranteed
in the current silicon revision. For complete securi-
ty, an external reset circuit must be added.
15.5.2 AVD not supported
On some devices with a specific VDD ramp up
speed the AVD may not start. As a result it cannot
generate interrupts when VDD rises and falls.
15.5.3 Internal RC oscillator operation
Internal RC oscillator operation is not supported in
ROM devices.
As a consequence, for cycle-accurate operations,
these configurations are prohibited in either input
or output mode.
Workaround:
To avoid this occurring, it is recommended to con-
nect one of these pins to GND (PD2 or PD4) or
VDD (PD1 or PD3).
182/185
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